MAX1204AEPP Maxim Integrated, MAX1204AEPP Datasheet - Page 17

• Manufacturer Part Number: MAX1204AEPP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1204AEPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Factory Pack Quantity: 18
• Voltage Reference: 4.096 V

Figure 12a. Timing Diagram for Power-Down Modes (External Clock)
Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)
The SHDN pin places the converter into full
power-down mode. Unlike the software power-down
modes, conversion is not completed; it stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference, which is not
shut down, is used. SHDN also selects internal or
external reference compensation (Table 7).
The MAX1204’s automatic power-down modes can
save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
Maxim Integrated
CLOCK
MODE
MODE
CLOCK
SHDN
DOUT
MODE
SSTRB
MODE
DOUT
DIN
DIN
INTERNAL
S X X X X X 1 1
S X X X X X 1 0
Power-Down Sequencing
SETS EXTERNAL
CLOCK MODE
(10 + 2 DATA BITS)
SETS INTERNAL
CLOCK MODE
CONVERSION
DATA VALID
POWERED UP
Hardware Power-Down
5V, 8-Channel, Serial, 10-Bit ADC
POWERED UP
DATA VALID
S
X
X
X
X
X
0 1
EXTERNAL
INTERNAL CLOCK MODE
with 3V Digital Interface
S
SETS FAST
POWER-DOWN
MODE
X
(10 + 2 DATA BITS)
X
Figure 14a depicts MAX1204’s power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01µF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
When exiting FULLPD, waiting this 2ms in FASTPD mode
(instead of just exiting FULLPD mode and returning to nor-
mal operating mode) reduces power consumption by a
factor of 10 or more (Figure 13).
X
DATA VALID
X
X
0 0
SETS FULL
POWER-DOWN
CONVERSION
POWER-DOWN
SETS EXTERNAL
FAST
500 Conversions per Channel per Second
CLOCK MODE
S
X X X X X
POWERED UP
1 1
DATA VALID
POWER-DOWN
FULL
MAX1204
Lowest Power at up to
EXTERNAL
POWER-
INVALID
DOWN
DATA
FULL
S
POWERED
UP
POWERED
UP
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