MAX1204AEPP Maxim Integrated, MAX1204AEPP Datasheet - Page 6

• Manufacturer Part Number: MAX1204AEPP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1204AEPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Factory Pack Quantity: 18
• Voltage Reference: 4.096 V

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TIMING CHARACTERISTICS
(V
MAX1204
6
Note 1: Tested at V
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with V
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
Note 11: Measured at V
Note 12: Measured at V
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
CS Rise to SSTRB Output
Disable (Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
DD
= +5V ±5%, V
calibrated.
REFADJ = GND.
active (CS low), the logic supply current depends on f
PARAMETER
L
= 2.7V to 3.6V, V
DD
SUPPLY
L
= 5.0V; V
= 2.7V and V
+5% and V
SS
= 0V; unipolar input mode.
SYMBOL
SS
t
L
SSTRB
t
t
t
t
t
t
ACQ
t
t
CSH
t
= 0V or -5V ±5%, T
t
t
CSS
t
SDV
SCK
t
STR
= 3.6V.
DH
DO
CH
DS
DV
CL
TR
SUPPLY
C
C
C
C
C
External clock mode only, C
External clock mode only, C
Internal clock mode only
LOAD
LOAD
LOAD
LOAD
LOAD
-5% only.
L
at 3.3V, and with all digital inputs tied to either V
= 100pF
= 100pF
= 100pF
= 100pF
= 100pF
SS
A
to V
= T
SCLK
CONDITIONS
MIN
DD
.
, and on the static and capacitive load at DOUT and SSTRB.
to T
MAX
, unless otherwise noted.)
LOAD
LOAD
= 100pF
= 100pF
MIN
100
100
200
200
1.5
20
0
0
L
or GND (Figure 12c);
TYP
MAX
240
240
240
240
240
240
Maxim Integrated
0
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns