MAX1281BCUP Maxim Integrated, MAX1281BCUP Datasheet - Page 10

• Manufacturer Part Number: MAX1281BCUP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1281BCUP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 559 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Serial 12-Bit ADCs with Internal Reference
Figure 1. Load Circuits for Enable Time
10
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
DOUT
PIN
1–8
10
11
12
13
14
15
16
17
18
19
20
______________________________________________________________________________________
9
a) High-Z to V
6k
CH0–CH7
REFADJ
SSTRB
NAME
SHDN
DOUT
SCLK
OH
COM
V
V
GND
REF
DIN
GND
CS
DD2
DD1
and V
OL
to V
OH
C
20pF
Sampling Analog Inputs
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a +2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
Analog and Digital Ground
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
Positive Supply Voltage
Positive Supply Voltage
LOAD
DD1
.
b) High-Z to V
DOUT
V
DD2
OL
and V
6k
C
GND
20pF
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6k
a) V
OH
GND
to High-Z
C
20pF
LOAD
Pin Description
DOUT
b) V
OL
V
DD2
to High-Z
6k
C
GND
20pF
LOAD
DD1
.