MAX1281BCUP Maxim Integrated, MAX1281BCUP Datasheet - Page 11

• Manufacturer Part Number: MAX1281BCUP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1281BCUP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 559 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX1280/MAX1281 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to microprocessors
(µPs). Figure 3 shows a functional diagram of the
MAX1280/MAX1281.
The equivalent input circuit of Figure 4 shows the
MAX1280/MAX1281’s input architecture, which is com-
posed of a T/H, input multiplexer, input comparator,
switched-capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 2 and 3.
The MAX1280/MAX1281 input configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) is connected to the sampling capacitor
while converting and must remain stable within ±0.5LSB
(±0.1LSB for best results) with respect to GND during a
conversion.
If a varying signal is applied to the selected IN-, its ampli-
tude and frequency must be limited to maintain accuracy.
The following equations determine the relationship
between the maximum signal amplitude and its frequency
Figure 3. Functional Diagram
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
REFADJ
SHDN
SCLK
COM
CH0
CH1
CH2
CH4
CH5
CH6
CH7
CH3
DIN
CS
REF
17
18
16
10
12
11
1
2
3
4
5
6
7
8
9
REGISTER
ANALOG
INPUT
INPUT
SHIFT
MUX
REFERENCE
+1.22V
______________________________________________________________________________________
CONTROL
LOGIC
Detailed Description
T/H
Pseudo-Differential Input
17kΩ
A
Serial 12-Bit ADCs with Internal Reference
+2.500V
≈ 2.05*
IN
CLOCK
12-BIT
CLOCK
SAR
ADC
REF
INT
OUT
MAX1280
MAX1281
REGISTER
OUTPUT
SHIFT
14
15
20
19
13
DOUT
SSTRB
V
V
GND
DD1
DD2
in order to maintain ±0.5LSB accuracy. Assuming a sinu-
soidal signal at IN-, the input voltage is determined by:
The maximum voltage variation is determined by:
A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB
of error when using a +2.5V reference voltage and a
2.5µs conversion time (15/f
voltage is used at IN-, connect a 0.1µF capacitor to
GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
sion interval begins with the input multiplexer switching
C
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V
resolution. This action is equivalent to transferring a
12pF x (V
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
Figure 4. Equivalent Input Circuit
HOLD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
max
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
*INCLUDES ALL INPUT PARASITICS
HOLD
from IN+ to IN-. This unbalances node ZERO at
d
INPUT
ν
IN
d
MUX
IN
as a sample of the signal at IN+. The conver-
GND
C
t
REF
+ - V
SWITCH
-
6pF
=
*
IN
(
ν
V
-) charge from C
DD1
IN
IN
C
12pF
-
- 2 f
HOLD
CAPACITATIVE
)
=
HOLD
/2 within the limits of 12-bit
(
π
V
DAC
TRACK
IN
SCLK
≤
- sin(2 ft)
ZERO
R
800Ω
)
IN
t
1LSB
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CONV
). When a DC reference
π
HOLD
V
=
DD1
/2
COMPARATOR
2 t
to the binary-
12
V
HOLD
REF
CONV
. The
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