MAX1292ACEG Maxim Integrated, MAX1292ACEG Datasheet - Page 13

• Manufacturer Part Number: MAX1292ACEG
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1292ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 50
• Voltage Reference: 2.5 V

can be used. At power-up, the MAX1290/MAX1292
enter the default external clock mode.
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and bit D6 must be set to 0; the internal clock frequency
is then selected, resulting in a 3.6µs conversion time.
When using the internal clock mode, connect the CLK
pin either high or low to prevent the pin from floating.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
CLK
CLK
WR
WR
CLK
CLK
WR
WR
with +2.5V Reference and Parallel Interface
ACQMOD = "1"
ACQMOD = "1"
t
CWH
______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
ACQMOD = "0"
ACQMOD = "0"
ACQUISITION STARTS
ACQUISITION STARTS
ACQUISITION STARTS
t
t
DH
DH
Internal Clock Mode
ACQUISITION STARTS
t
CWS
t
CH
t
CP
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
t
CL
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
ACQUISITION ENDS
ACQUISITION ENDS
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6a shows the
clock and WR timing relationship for internal and exter-
nal (Figure 6b) acquisition modes with an external
clock. Proper operation requires a 100kHz to 7.6MHz
clock frequency with 30% to 70% duty cycle. Operating
the MAX1290/MAX1292 with clock frequencies lower
than 100kHz is not recommended, because it causes a
voltage droop across the hold capacitor in the T/H
stage that results in degraded performance.
ACQUISITION ENDS
t
CWH
ACQUISITION ENDS
CONVERSION STARTS
ACQMOD = "0"
CONVERSION STARTS
ACQMOD = "0"
t
CWS
External Clock Mode
CONVERSION STARTS
CONVERSION STARTS
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