ispLSI 1032-60LJI Lattice, ispLSI 1032-60LJI Datasheet
ispLSI 1032-60LJI
Specifications of ispLSI 1032-60LJI
Related parts for ispLSI 1032-60LJI
ispLSI 1032-60LJI Summary of contents
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... Product Line Ordering Part Number ispLSI 1032-60LT ispLSI 1032-80LT ispLSI 1032-90LT ispLSI 1032-60LTI ispLSI 1032-60LJ ispLSI 1032 ispLSI 1032-80LJ ispLSI 1032-90LJ ispLSI 1032-60LJI ispLSI 1016-60LH/883 5962-9476201MXC 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Phone (503) 268-8000 Internet: http://www.latticesemi.com ...
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... The basic unit of logic on the ispLSI 1032 device is the Generic Logic Block (GLB). The GLBs are labeled A0 (see figure 1). There are a total of 32 GLBs in the ispLSI 1032 device ...
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... GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1032 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution ...
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... A SYMBOL PARAMETER C 1 Dedicated Input Capacitance C I/O and Clock Capacitance Guaranteed but not 100% tested. Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1032 1 +1.0V CC +1.0V CC Commercial T = 0°C to +70°C A Industrial T = -40°C to +85°C A Military/883 T = -55°C to +125°C ...
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... Refer to the Power Consumption sec- CC tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1032 Figure 2. Test Load GND to 3.0V ≤ 3ns 10% to 90% 1.5V 1.5V ...
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... Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. Specifications ispLSI 1032 Over Recommended Operating Conditions 1 3 ...
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... ORP Bypass Delay orpbp 46 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1032 -90 -80 -60 MIN. MAX. ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line 54 Global Reset Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1032 1 7 -90 -80 -60 MIN. MAX. MIN. MAX. MIN. MAX. ...
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... Clock (max) + Reg co + Output ( gy0(max) + gco + ( ) ( = #50 + #40 + #52 + #40 19 (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0) 1. Calculations are based upon timing specifications for the ispLSI 1032-80. Specifications ispLSI 1032 GRP GLB Feedback GRP Bypass GLB Reg Bypass #28 #33 GRP 20 PT Loading XOR Delays Delay #34, 35, 36 #27, 29, ...
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... I CC can be estimated for the ispLSI 1032 using the following equation PTs * 0.30 nets * Max. freq * 0.009) where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The I CC estimate is based on typical conditions ( ...
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... SCLK/ RESET GND Pins have dual function capability Specifications ispLSI 1032 Input/Output Pins - These are the general purpose I/O pins used by the 28, 29, logic array. 32, 33, 36, 37, 40, 41, 47, 48, 51, 52, 55, 56, 59, 60, 70, 71, 74, ...
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... Y3 61 GND 13 Pins have dual function capability 2. NC pins are not to be connected to any active signals, Vcc or GND. Specifications ispLSI 1032 19, 20, Input/Output Pins - These are the general purpose I/O pins used by the 23, 28, logic array. 31, 32, 35, 36, 42, ...
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... G3 GND C6, F3 F2, F11 1. Pins have dual function capability pins are not to be connected to any active signals, Vcc or GND. Specifications ispLSI 1032 Input/Output Pins - These are the general purpose I/O pins used by the H2, J1, logic array. L1, K2, L3, K4, K5, L5, L6, ...
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... Pin Configuration ispLSI 1032 84-Pin PLCC Pinout Diagram VCC 21 GND 22 ispEN 23 RESET 24 *SDI *Pins have dual function capability ...
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... Pin Configuration ispLSI 1032 100-pin TQFP Pinout Diagram VCC 12 GND 13 ispEN 14 RESET 15 2 SDI pins are not to be connected to any active signal, Vcc or GND. ...
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... Pin Configuration ispLSI 1032/883 84-Pin CPGA Pinout Diagram I/O38 I/O41 I/O42 I/O36 I/O39 I/O40 I/O35 I/O37 I/O33 I/O34 Y1 IN4 I/O32 Vcc I/O31 GND *SCLK IN3 I/O30 I/O29 I/O28 I/O26 I/O27 I/O25 I/O23 I/O24 I/O22 I/O21 *Pins have dual function capability. ...
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... INDUSTRIAL t Ordering Number max (MHz) pd (ns ispLSI 1032-60LJI 60 20 ispLSI 1032-60LTI MILITARY/883 t Ordering Number pd (ns) 20 ispLSI 1032-60LG/883 16 X Grade Blank = Commercial I = Industrial /883 = 883 Military Process Package J = PLCC T = TQFP ...