MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet
MAX11359AETL
Specifications of MAX11359AETL
Available stocks
Related parts for MAX11359AETL
MAX11359AETL Summary of contents
Page 1
... Monitors DD o SPI/QSPI/MICROWIRE, 4-Wire Serial Interface o Space-Saving (6mm x 6mm x 0.75mm), 40-Pin TQFN Package Ordering Information PART TEMP RANGE MAX11359AETL+ -40°C to +85°C MAX11359ACTL+* 0°C to +70°C + Denotes a lead(Pb)-free/RoHS–compliant package. * Future product—contact factory for availability Exposed pad. Pin Configuration ...
Page 2
... A REG = +25°C.) (Note 1) A MIN TYP 16 10 Table 1 ±0.004 ±1.0 ±2.0 ±10 ±0.6 ±0.003 ±1 1. 10µ CPOUT MAX UNITS Bits 512 sps µV RMS %FSR %FSR ±0.003 µV/°C %FSR ppm/ ° Maxim Integrated ...
Page 3
... Input Leakage Current at SWA/B Input Leakage Current at FBA/B DAC Output Buffer Leakage Current Input Common-Mode Voltage Line Regulation Load Regulation Output Voltage Range Maxim Integrated = +1.25V, external reference, CLK32K = 32.768kHz (external clock), C REF = unless otherwise noted. Typical values are at T MIN MAX ...
Page 4
... AGND 2.5 1.238 1.251 1.976 1.996 2.349 2.422 SOURCE to 500µ SINK 1.7 50µA = 10µ CPOUT MAX UNITS V/ms µs µV P-P mA Ω 150 ns µ AVDD MΩ 100 nA 1.264 2.016 V 2.495 50 o ppm µA 100 µV/V 1.2 µV/µA Maxim Integrated ...
Page 5
... V L Input Offset Voltage Offset-Error Tempco Input Bias Current (Note 7) Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Maxim Integrated = +1.25V, external reference, CLK32K = 32.768kHz (external clock), C REF = unless otherwise noted. Typical values are at T MIN MAX SYMBOL ...
Page 6
... 0°C to +50° AGND 100 = 10µ CPOUT MAX UNITS dB dB 0.005 0.025 0.05 0.25 0.5 V 0.005 0.025 0.05 0.25 0.5 kHz Degrees V/µs µV P-P mA µ Ω 150 ±1 nA ±600 pA ±400 ±2 ±1.2 nA ±0.8 ±2 ±1.2 nA ±0 AVDD ns Maxim Integrated ...
Page 7
... VOLTAGE MONITORS DVDD Monitor Supply Voltage Range Trip Threshold (V Falling) DVDD DVDD Monitor Timeout Reset Period DVDD Monitor Hysteresis Maxim Integrated = +1.25V, external reference, CLK32K = 32.768kHz (external clock), C REF = unless otherwise noted. Typical values are at T MIN MAX SYMBOL CONDITIONS SNO_, SNC_, or SCM_ = AVDD or AGND ...
Page 8
... MAX UNITS 5 ms 1.0 3.6 V 2.7 2.8 2 1.7 V 32.768 kHz 25 ppm 1500 32.768 kHz 4.8660 4.9152 4.9644 2.4330 2.4576 2.4822 MHz 1.2165 1.2288 1.2411 608.25 614.4 620.54 kHz 0. ± DVDD 0 DVDD Maxim Integrated ...
Page 9
... RESET Output Leakage Current UPIO_ Output Low Voltage UPIO_ Output High Voltage POWER REQUIREMENT Analog Supply Voltage Range Digital Supply Voltage Range Maxim Integrated = +1.25V, external reference, CLK32K = 32.768kHz (external clock), C REF = unless otherwise noted. Typical values are at T MIN ...
Page 10
... SWA A REG = +25°C.) (Note 1) A MIN TYP = V = AVDD DVDD 1. AVDD DVDD 1.15 1. AVDD DVDD = V = AVDD DVDD = V = AVDD DVDD 4. AVDD DVDD 5.56 = -40°C to +85° +25°C 1 -40°C are guaranteed by design 10µ CPOUT MAX UNITS 2.0 mA 1.7 1.3 6.5 9 µA 4 µA Maxim Integrated ...
Page 11
... Table 3. Maximum External Source Impedance Without 16-Bit Gain Error PARAMETER 0 (Note 15) Resistance (kΩ) 350 Note 15: 2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance. Maxim Integrated OUTPUT NOISE (µV GAIN = 2 1.684 3.178 3.234 3.307 55.336 104.596 587.138 983 ...
Page 12
... MAX 0 10 100 1 7.82 1.95 2.93 rises above the reset threshold. This is largely DD monitor output, and the DD going high or the external RESET going high, DD Maxim Integrated = 10µF, UNITS MHz µs µs ms µ ...
Page 13
... AVDD REF DVDD SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE 700 NORMAL MODE CLK BUFFER DISABLED 600 500 400 300 200 1.8 2.1 2.4 2.7 3.0 3.3 V (V) DVDD Maxim Integrated t t CYC 6kΩ = 50pF AND HIGH IMPEDANCE OL Typical Operating Characteristics = 10µ +25° ...
Page 14
... FUNCTIONS DISABLED 0 3.0V DVDD 0 1.8V DVDD 0.4 0 -40 -15 10 TEMPERATURE (°C) AVDD SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE 2.0 SLEEP MODE, ALL FUNCTIONS DISABLED 1.8 1.6 1.4 1.2 1.0 3.3 3.6 1.8 2.1 2.4 2.7 V AVDD AVDD SUPPLY CURRENT vs. TEMPERATURE 2.0 SLEEP MODE, ALL FUNCTIONS DISABLED 1.8 1 3.0V AVDD 1.4 V AVDD 1.2 1.0 -40 - TEMPERATURE (° 3.0 3.3 3.6 ( Maxim Integrated ...
Page 15
... VOLTAGE vs. TEMPERATURE 1.0010 1.0005 1.0000 0.9995 0.9990 0.9985 0.9980 0.9975 V = 1.25V REF 0.9970 -40 - TEMPERATURE (°C) Maxim Integrated Typical Operating Characteristics (continued) = 10µ +25°C, unless otherwise noted.) A CPOUT INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 2.60 2.55 FLL DISABLED 2.50 2.45 FLL ENABLED 2.40 2.35 2.30 2.25 CLK = 2.4576MHz 2 ...
Page 16
... FREQUENCY (Hz) DAC INL vs. OUTPUT CODE 0.25 0.15 0.05 -0.05 -0.15 -0.25 0 200 400 60 85 OUTPUT CODE DAC DNL vs. OUTPUT CODE 0. 3.0V AVDD V = 2.5V 0.15 REF 0.10 0.05 0 -0.05 -0. 1.8V -0.15 AVDD V = 1.25V REF -0.20 800 1000 0 200 400 OUTPUT CODE V = 2.048V REF 100 1k 10k V = 1.8V AVDD V = 1.25V REF 600 800 1000 600 800 1000 Maxim Integrated ...
Page 17
... SOURCE CURRENT (mA) DAC FBA/B INPUT BIAS CURRENT vs. TEMPERATURE 1.8V AVDD V = 0.5V AIN -40 - TEMPERATURE (°C) Maxim Integrated Typical Operating Characteristics (continued) = 10µ +25°C, unless otherwise noted.) A CPOUT DAC DNL vs. OUTPUT CODE 0.20 0.15 0.10 0.05 0 -0.05 -0. 3.0V AVDD -0. 2.5V REF -0.20 0 200 400 ...
Page 18
... CM 7 3.0V 6.9 AVDD 6 1.8V AVDD 6.3 6.0 -40 - TEMPERATURE (°C) OP-AMP INPUT BIAS CURRENT vs. TEMPERATURE 3.0V AVDD -40 - TEMPERATURE (°C) OP-AMP OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT 3.00 2.96 2.92 2.88 2. 3.0V AVDD UNITY GAIN IN_ AVDD 2.80 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 SOURCE CURRENT (mA) Maxim Integrated ...
Page 19
... V (V) AVDD SPDT ON-RESISTANCE vs. V VOLTAGE COM 3.0V AVDD 1.8V AVDD 25 0 0.5 1.0 1.5 V (V) COM Maxim Integrated Typical Operating Characteristics (continued) = 10µ +25°C, unless otherwise noted.) A CPOUT + = 0.5V IN_ 3.0 3.3 3.6 2.0 2.5 3.0 MAX11359A OP-AMP OUTPUT VOLTAGE vs. TEMPERATURE 501.0 UNITY GAIN 0.5V IN_ R = 10kΩ L 500 ...
Page 20
... COM -40 - TEMPERATURE (°C) SPDT/SPST SWITCHING TIME vs. AVDD SUPPLY VOLTAGE OFF 20 15 1.8 2.1 2.4 2.7 3.0 3.3 3.6 V (V) AVDD SPDT/SPST SWITCHING TIME vs. TEMPERATURE 3.0V AVDD OFF 19 15 -40 - TEMPERATURE (°C) Maxim Integrated ...
Page 21
... OUT 3.10 -40 - TEMPERATURE (°C) CHARGE-PUMP OUTPUT VOLTAGE RIPPLE vs. OUTPUT CURRENT OUTPUT CURRENT (mA) Maxim Integrated Typical Operating Characteristics (continued) = 10µ +25°C, unless otherwise noted.) A CPOUT 1.8V DVDD 8 10 MAX11359A CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT 3.6 3.5 3 ...
Page 22
... Amplifier 1 Inverting Input. Analog input to mux. 22 IN1+ Amplifier 1 Noninverting Input 23 SWA DACA SPST Shunt Switch Input. Connects to OUTA through a SPST switch. 24 FBA DACA Force-Sense Feedback Input. Analog input to mux. 22 FUNCTION ) after DVDD rises above the 1.8V threshold. RESET also pulses low DSLP Pin Description Maxim Integrated ...
Page 23
... Digital Ground. Also ground for cascaded linear voltage regulator and charge-pump doubler. 40 UPIO1 U ser - Inp ut/O utp the U P IO1_C TRL Reg i ster for functionality. — osed Leave unconnected or connect to AGN D . Maxim Integrated MAX11359A Pin Description (continued) FUNCTION 23 ...
Page 24
... CPOUT (2.7V) VOLTAGE MONITOR CHARGE- PUMP DVDD M32K DOUBLER LINEAR 1.65V VOLTAGE REGULATOR PGA 1.25V BANDGAP 1.6384, 2 V/V REF 10-BIT DAC BUF HFCLK OP2 IN2+ IN2- AGND UPIO1 UPIO2 UPIO3 UPIO4 RESET CPOUT CF+ CF- REG REF OUTA SWA FBA OUT2 Maxim Integrated ...
Page 25
... ADC. Bits GAIN1 and GAIN0 set the gain (see the ADC Register for more information). The PGA gain is implemented in the digital filter of the ADC. Maxim Integrated The MAX11359A performs analog-to-digital conversions using a single-bit, 3rd-order, switched-capacitor sigma- delta modulator. The sigma-delta modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information ...
Page 26
... ESRs, as shown below. R OUT 80 100 120 Force-Sense DAC SWITCH = DROOP OUT OUT ESR SWITCH f C CLK F I OUT = + RIPPLE OUT f C CLK CPOUT Charge Pump = CLK = 5Ω), and + ESR CPOUT ESR C CPOUT Maxim Integrated ...
Page 27
... AVDD and DVDD are not connected together require a separate external voltage monitor for AVDD. See Figure 7 for a block diagram of the DVDD voltage supervisor. The second voltage monitor tracks the charge-pump output voltage, CPOUT. If CPOUT falls below the 2.7V Maxim Integrated M32K 1.65V REG REG Figure 6 ...
Page 28
... LSBs of the 32-bit second counter. The ADE bit automatically clears when the time-of-day alarm trips. The time-of-day alarm causes the device to exit sleep mode. RSTE DVDD (1.8V) VOLTAGE MONITOR that is larger than the load capacitance of L Real-Time Clock (RTC) Time-of-Day Alarm RESET LDVD Maxim Integrated ...
Page 29
... POR PULSES HIGH DURING POWER-UP. WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE. 32K WDE Figure 11. Watchdog Timer Block Diagram Maxim Integrated Watchdog frequency clock is locked to the 32.768kHz reference. If the FLL is disabled, the high-frequency clock is free- running. At power-up, the CLK pin defaults to a 2.4576MHz clock output, which is compatible with most µ ...
Page 30
... CONTROLLED INTEGRATOR OSCILLATOR AIN1 AIN2 Figure 13. Temperature-Sensor Measurement Block Diagram CKSEL2 CKSEL<1:0> CLKE 0 2 MUX DIVIDER 1 4.9152MHz HFCLK CRDY 4.9152MHz HF OSCILLATOR AND FLL PROGRAMMABLE CURRENT SOURCE CURRENT IVAL<1:0> SOURCE 1:3 IMUX<1:0> DEMUX TEMP SENSOR Maxim Integrated CLK AIN1 AIN2 TEMP+ TEMP- ...
Page 31
... This results in the currents I 2 and 120µA (typ the case of the two current method, two measurements per current are Maxim Integrated Two-Current Method used to improve accuracy by precisely measuring the and I are values of the currents Current I resistor R, and the voltage is measured across the diode using the ADC as NVBE1 ...
Page 32
... For SPI passthrough mode, see the UPIO_SPI Register section. An address byte identifies each register. Table 4 shows the complete register address map for this family of DAS. Figures 14, 15, and 16 provide timing dia- grams for read and write commands. Pulse-Width Modulator (PWM) Serial Interface Maxim Integrated ...
Page 33
... Figure 15. Serial-Interface Register Read with 8-Bit Control Word Followed by a Variable Length Data Read CS SCLK DIN DOUT DRDY X = DON’T CARE. Figure 16. Performing an ADC Conversion (DRDY Function can be Accessed at UPIO Pins) Maxim Integrated ...
Page 34
... LSDE CPDE HYSE RSTE CRDY ADD UPF<4:1> GAIN<1:0> DACA<9:8> DACB<9:8> FLLE HFCE INTP WDE SWBH SWBL ALH4 LL4 ALH3 LL3 ALH2 LL2 ALH1 LL1 MALD MALS X X ALD ALS Maxim Integrated ...
Page 35
... ADC and SDC inputs, and the neg- ative mux output to the negative ADC and SDC inputs. POL = 1 sets the positive mux output to the negative ADC and SDC inputs, and the negative mux output to the positive ADC and SDC inputs. Maxim Integrated BIP POL CONT MODE<2:0> ...
Page 36
... CONVERSION MODE 406.3489583 Normal 477.0183424 System Offset Calibration System Gain Calibration Normal Normal Self Offset Calibration Self Gain Calibration Self Offset and Gain Calibration MODE2 MODE1 MODE0 Maxim Integrated ...
Page 37
... Open Don’t care. Maxim Integrated MUXP1 MUXP0 MUXN3 specified by the RATE<2:0> bits until CONT deasserts or ADCE deasserts, powering down the ADC. When a conversion initiates using the S bit, the STRT bit asserts and deasserts automatically after the initial conversion completes ...
Page 38
... GAIN CAL register digital- scaling range by the internal noise of the ADC. ADC10 ADC9 ADC8 LSB ADC2 ADC1 ADC0 OFFSET18 OFFSET17 OFFSET16 OFFSET10 OFFSET9 OFFSET8 LSB OFFSET2 OFFSET1 OFFSET0 GAIN18 GAIN17 GAIN16 GAIN10 GAIN9 GAIN8 LSB GAIN2 GAIN1 GAIN0 Maxim Integrated ...
Page 39
... ADCE in the ADC register and DAE/OP3E, OP2E, and OP1E bits in the DACA_OP registers, powering down these analog blocks. Setting AOFF = 0 has no effect. The AON bit has priority when both AON and AOFF bits are asserted. Maxim Integrated OP1E X X DACA5 DACA4 DACA3 DAE: DACA enable bit ...
Page 40
... UPIO pins. When configured this way the MALD bit does not mask the UPIO alarm output. NOMINAL TSEL2 TSEL1 100 1 150 1 200 1 ASEC14 ASEC13 ASEC6 ASEC5 X X TSEL0 ASEC12 ASEC4 LSB X Maxim Integrated ...
Page 41
... RWE: RTC write-enable bit. Set RWE = 1 prior to writing to the RTC register and the RTCE bit in this register. If RWE = 0, all writes are prevented to the RTC register as well as the RTCE bit in this register. The RWE signal takes effect after the rising edge of the 16th clock; Maxim Integrated X RWE RTCE CKSEL0 ...
Page 42
... XTAL XTAL attached XTAL CKSEL2 CKSEL1 (kHz) 4915 2457 1228 614 32.768 1 0 16.384 1 0 8.192 1 1 4.096 1 1 FLL, C/P, SDC INPUT ADC CLOCK SOURCE SOURCE XTAL FLL/HFCLK CLK32K FLL/HFCLK CKSEL0 Maxim Integrated ...
Page 43
... RTC value. Due to the asynchro- nous nature of RTC reads possible to have a maximum 1s error between the actual and reported times from the time-of-day clock. To prevent the data from changing during a read operation, complete reads Maxim Integrated SEC29 SEC28 SEC27 SEC21 ...
Page 44
... SPDT2 switch, and set SPD2 = 0 to disable the PWM output controlling the SPDT2 switch. The SPDT2<1:0> bits, the UPIO pins (if programmed), and the PWM out- put (if enabled), determine the SPDT2-switch state. See Table 19 for more details. The power-on default is 0. SWAL X X LSB Maxim Integrated ...
Page 45
... PWMTP<7:0>: PWM time period bits. These bits con- trol the PWM output period defined. The PWM output period is defined as: (PWMTP<7:0> + 1)/(PWM input frequency) Set the PWM input frequency by selecting the FSEL<2:0> bits as described in Table 14. The power- on default is 00 hex. Maxim Integrated PWMTH5 PWMTH4 PWMTH3 PWMTP5 PWMTP4 PWMTP3 Writing to the WATCHDOG register address sets the watchdog timer to 0ms ...
Page 46
... Off SDCE Off ADE ADE RTCE RTCE OSCE SOSCE CK32E SCK32E HFCE Off CLKE Off FLLE Off WDE Off PWME SPWME LDOE Off CPE Off CPDE Off LSDE LSDE HYSE HYSE Off UP_MD<3:0> PUP_ PUP_ SV_ SV_ ALH_ ALH_ Maxim Integrated ...
Page 47
... CLOCK 2-BIT COUNTER X SPI WRITES WDE = 1 RESET Figure 17. Watchdog Timer Architecture Maxim Integrated SPWME SHDN SPWME: Sleep-mode PWM enable bit. SPWME = 1 enables the internal PWM in sleep mode, and SPWME = 0 disables it in sleep mode, regardless of the state of the PWME bit. Input frequencies are limited to 32.768kHz or lower since the high-frequency clock is disabled in sleep mode ...
Page 48
... GPO, LL3 = 0 sets the output to a logic-low and LL3 = 1 sets the output to a logic-high. A read of LL3 returns the voltage level at the UPIO3 pin at the time of the read, regardless of how it is programmed. The power-on default is 0. LSB SV4 ALH4 LL4 LSB SV3 ALH3 LL3 Maxim Integrated ...
Page 49
... DVDD as the supply voltage for the UPIO1 pin, and set SV1 = 1 to select CPOUT as the supply voltage. The selected supply voltage applies to all modes for the UPIO1 pin. The power-on default is 0. Maxim Integrated UP2MD1 UP2MD0 PUP2 ALH2: Active logic-level assertion high UPIO2 bit. Set ALH2 = 0 to define the input or output assertion level for UPIO2 as low except when in GPI and GPO modes ...
Page 50
... SHDN input. RTC alarm digital output. Asserts for time-of-day alarm events; equivalent to ALD in STATUS register. Reserved. Do not use these settings. ADC data-ready digital output. Asserts when analog-to-digital conversion or calibration completes. Not masked by MADD bit. DESCRIPTION Maxim Integrated ...
Page 51
... UPIO3 SET BY UPIO2_CTRL REGISTER UPIO2 SET BY UPIO1_CTRL REGISTER UPIO1 Figure 18. SPI Pass-Through Timing Diagram Maxim Integrated UP2S UP1S UP4S: UPIO4 SPI pass-through-mode enable bit. A logic 1 maps the inverted CS signal to the UPIO4 pin. Therefore, UPIO4 is low (near DGND) when SPI pass- through mode is active, and is high (near DVDD or CPOUT) when the mode is inactive ...
Page 52
... SNO2 open, SNC2 open SNO2 closed, SNC2 closed SNO2 closed, SNC2 closed SNO2 closed, SNC2 closed SNC2 closed, SNO2 open SNC2 open, SNO2 closed SNC2 open, SNO2 closed SNC2 open, SNO2 closed LSB X Maxim Integrated ...
Page 53
... ACTUAL MEAS GAIN OFFS optimized for an internal voltage reference of 1.25V using the four-current method. The power-on default varies. Maxim Integrated IVAL1 IVAL0 IVAL<1:0>: Internal current-source value bits. Selects the value of the internal current source as shown in Table 21. The power-on default is 00. Table 21. Setting the Current Level ...
Page 54
... HYSE = 0 to set the hysteresis to +20mV. On initial power-up, the hysteresis is +20mV and can be pro- grammed to 200mV once RESET goes high. Once pro- grammed to +200mV, the DVDD falling threshold is +1.8V nominally and the rising threshold is +2.0V nominally. The MADD MALD X LSB MUPF3 MUPF2 MUPF1 LSB RSTE X X Maxim Integrated ...
Page 55
... Otherwise the LCPD bit reasserts immediately. LCPD = 0 when the CPOUT low voltage detector is disabled. The power-on default is 0. Maxim Integrated RSTE: RESET output enable bit. Set RSTE = 1 to enable RESET to be controlled by the +1.8V DVDD low- supply-voltage detector, and set RSTE = 0 to disable this control ...
Page 56
... Exit sleep mode and enter normal mode by one of the following methods: • With the SHDN bit = 0, deassert the SLEEP or SLEEP function on UPIO, only if SLEEP or SLEEP function is used for entering sleep mode. Power-On Reset or Power-Up Power Modes Sleep Mode Maxim Integrated ...
Page 57
... DRDY LO HI DOUT THREE-STATED SCLK, DIN LO Figure 19. Initial Power-Up, Sleep Mode, and Wake-Up Timing Diagram with V Maxim Integrated INITIAL POWER, WAKE-UP, AND SLEEP XTAL B/W 32KIN AND 32KOUT PIN 1.8V 1.8V OSCE = 1 CK32E = 1 INTERNAL EXTERNAL OUTPUT DISABLED, BUT PULLED LOW INTERNAL t DFON ...
Page 58
... INPUT VOLTAGE (LSB) MAX11359A DAC A Supply Voltage Measurement Gain x 65536)/N AVDD REF is the reference voltage for the ADC, Gain REF > V AVDD V /GAIN REF +32,765 +32,767 FBA OUTA x Gain). This REF Maxim Integrated ...
Page 59
... REF 0111 1111 11 0000 0000 01 0000 0000 00 Maxim Integrated 10kΩ FBA 10kΩ OUTA Figure 24. DAC Bipolar Output Circuit In unipolar mode, the output code ranges from 0 to 65,535 for inputs from zero to full-scale. In bipolar ...
Page 60
... V BATT1 MAX11359A Figure 26. Input Multiplexer Temperature Measurement with Two Remote Sensors Programmable-Gain Instrumentation PWM Applications ADC Calibration V BATT2 GPIOn UPIO1 NOTE: MAX11359A GPIOn IS LOW = LED ON, x2 HIGH-Z = LED OFF BATTVCHECK < 0.6125V AIN1 V = 1.25V REF µP Amplifier BACKLIGHT V DD Maxim Integrated ...
Page 61
... CS2 MEM RESET INPUT UP INPUT INPUT HIGH-FREQUENCY MICRO CLOCK DOWN X2IN INPUT 32KIN Figure 27. Optical Reflectometry Application with Dual LED and Single Photodiode Maxim Integrated V CP SERIAL-PORT INTERFACE V SS EEPROM SCK CS MAX11359A DIN DOUT SCLK CS2 CS ...
Page 62
... The more the crystal is isolat- ed from other signals on the board, the less likely it is that noise will be coupled into the crystal. Maintain a minimum distance of 5mm between any digital signal and any trace connected to 32KIN or 32KOUT. Crystal Layout Maxim Integrated ...
Page 63
... UPIOs, RTC, Voltage Monitors, and Temp Sensor 2N3904 2N3904 Figure 28. Temperature Measurement with Two Remote Sensors IN1+ V IN+ IN1- SCM1 IN2+ V IN- IN2- SCM2 MAX11359A Figure 29. Programmable-Gain Instrumentation Amplifier Maxim Integrated AIN1 MUX PGA 16-BIT ADC AGND AIN2 MUX AGND TEMP 1.25V SENSOR REF 5) Place a local ground plane on the PCB layer imme- diately below the crystal guard ring ...
Page 64
... Figure 31. Sensor-Bias Voltage Trim Application µC SEG n LCD LCD DRIVERS COM m ~1.25V REF MAX11359A RIPPLE < 1mV SNO1 350kΩ SCM1 PWM SNC1 SPDT1 0.1µF AGND IN1+ IN1- OUT1 I T TRANSDUCER ~19kHz VOLTAGE 240kΩ ~0.3V 60kΩ 0.300V (±1mV) Maxim Integrated ...
Page 65
... Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX11359A PWM Figure 32. Power-Supply Sleep-Mode Duty-Cycle Control Figure 33. Single-Ended Piezoelectric Buzzer Drive Maxim Integrated AVDD DVDD DVDD CPOUT SV_ MUX V BATT 10MΩ UPIO_ PSCTL PSCTL EN_ +3.3V V ALH_ DD +2 ...
Page 66
... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 TQFN-EP 1kHz TO 8kHz TYP CPOUT + 6.4V DIFF - -CPOUT 1kHz TO 8kHz TYP Package Information PACKAGE OUTLINE NO. CODE T4066+5 21-0141 LAND PATTERN NO. 90-0055 Maxim Integrated ...
Page 67
... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...