MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 47

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

The SLEEP_CFG register allows users to program spe-
cific behavior for the 32kHz oscillator, buffer, and PWM
in sleep mode. It also contains a sleep-control bit (SLP)
to enable sleep mode.
SLP (ADR0): Sleep bit. The SLP bit is the LSB in the
SLEEP_CFG address control byte. Set SLP = 1 to
assert the SHDN bit and enter sleep mode. Writing the
register with SLP = 0 or reading with SLP = 0 or SLP =
1 has no effect on the SHDN bit.
SOSCE: Sleep-mode 32kHz crystal oscillator enable
bit. SOSCE = 1 enables the 32kHz oscillator in sleep
mode, and SOSCE = 0 disables it in sleep mode,
regardless of the state of the OSCE bit. The power-on
default is 1.
SCK32E: Sleep-mode CK32K-pin output-buffer enable
bit. SCK32E = 1 enables the 32kHz output buffer in
sleep mode, and SCK32E = 0 disables it in sleep
mode, regardless of the state of the CK32E bit. The
power-on default is 1.
SLEEP_CFG Register (Power-On State: 1100 XXXX)
Figure 17. Watchdog Timer Architecture
Maxim Integrated
SLP (ADR0)
UPIOs, RTC, Voltage Monitors, and Temp Sensor
32K
16-Bit Data-Acquisition System with ADC, DAC,
2-BIT COUNTER
SPI WRITES
4Hz CLOCK
WDE
RESET
SOSCE
MSB
X
BY-8192
DIVIDE-
SCK32E
WDW
WDE = 1
POR
4Hz
0
D
CK
SPWME
1
R
WATCHDOG
ADDRESS
Q
Q
2
0
SHDN
WATCHDOG
ADDRESS
1
SPWME: Sleep-mode PWM enable bit. SPWME = 1
enables the internal PWM in sleep mode, and SPWME
= 0 disables it in sleep mode, regardless of the state of
the PWME bit.
Input frequencies are limited to 32.768kHz or lower
since the high-frequency clock is disabled in sleep
mode. SOSCE must be asserted to have 32kHz avail-
able as an input to the PWM. The power-on default is 0.
SHDN: Shutdown bit. This bit is read only. SHDN is
asserted by writing to the SLEEP register address or by
writing to the SLEEP_CFG register with SLP = 1. When
SHDN is asserted, the device is in sleep mode even if
the SLEEP or SLEEP function on the UPIO is deassert-
ed. The SHDN bit is deasserted by writing to the
NORM_MD register or by other defined events. Events
that cause SHDN to be deasserted are a day alarm or
an edge on the UPIO wake-up pin causing wake-up to
be asserted. The power-on default is 0.
0
D
CK
750ms
R
1
Q
Q
X
2
250ms
3
0
X
WATCHDOG TIMER
MAX11359A
1
WATCHDOG
ADDRESS
2
X
0
LSB
RESET
X
47