MAX1068BEEG Maxim Integrated, MAX1068BEEG Datasheet - Page 18

• Manufacturer Part Number: MAX1068BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1068BEEG

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
prior to the rising edge of CS, cause zeros to be
clocked out of DOUT. The MAX1068 external clock 16-
bit-wide data-transfer mode requires 32 SCLK cycles for
completion (Figure 11).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Force DSPR high and DSEL low (MAX1068) for the SPI/
QSPI/MICROWIRE-interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to
clock in data (Figure 12). DOUT changes from high-Z
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
18
INTERNAL
STATE
STATE
DOUT
DSPR
DOUT
SCLK
DSEL
SCLK
______________________________________________________________________________________
ADC
ADC
CLK
EOC
DIN
DIN
CS
CS
Internal Clock 8-Bit-Wide Data-Transfer and
X = DON
MSB
X = DON
DSPR = DV
MSB
1
CSW
1
,
T CARE
,
T CARE
Scan Mode (MAX1067 and MAX1068)
). Forcing CS high in the middle of a
DD
, DSEL = GND (MAX1068 ONLY)
LSB
1
8
LSB
0
8
t
ACQ
X
2
X
t
ACQ
X
X
6
X
X
X
• • •
t
CONV
X
16
MSB
to logic low after CS is brought low. Input data latches
on the rising edge of SCLK. The command/configura-
tion/control register begins reading DIN on the first
SCLK rising edge and ends on the rising edge of the
8th SCLK cycle. The MAX1067/MAX1068 select the
proper channel for conversion on the rising edge of the
3rd SCLK cycle. The internal oscillator activates 125ns
after the rising edge of the 8th SCLK cycle. Turn off the
external clock while the internal clock is on. Turning off
SCLK ensures the lowest noise performance during
acquisition. Acquisition begins on the 2nd rising edge
of the internal clock and ends on the falling edge of the
6th internal clock cycle. Each bit of the conversion
result shifts into memory as it becomes available. The
conversion result is available (MSB first) at DOUT on
the falling edge of EOC. The internal oscillator and ana-
log circuitry are shut down on the high-to-low EOC tran-
25
IDLE
MSB
9
POWER-DOWN
t
CONV
24
16
LSB
LSB
S1 S0
S1 S0
32
24
IDLE
X