MAX1068BEEG Maxim Integrated, MAX1068BEEG Datasheet - Page 28

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MAX1068BEEG

Manufacturer Part Number
MAX1068BEEG
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1068BEEG

Number Of Channels
8
Architecture
SAR
Conversion Rate
200 KSPs
Resolution
14 bit
Input Type
Single-Ended
Snr
84 dB
Interface Type
QSPI, Serial (SPI, Microwire)
Operating Supply Voltage
2.7 V to 5.25 V, 4.75 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Package / Case
QSOP-24
Maximum Power Dissipation
762 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.096 V
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
V
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1067/MAX1068 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN_ and REF after AV
• DV
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
28
5
are the 2nd- through 5th-order harmonics.
present.
______________________________________________________________________________________
DD
T
1
HD
is independent of the supply sequencing.
is the fundamental amplitude and V
=
Supplies, Layout, Grounding, and
20
Spurious-Free Dynamic Range
×
log
Total Harmonic Distortion
V
2
2
+ V
3
2
V
+ V
1
DD
4
2
+ V
and AGND are
5
Bypassing
2
2
through
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV and a 1 LSB error with a +4.096V
full-scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AV
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
Figure 25. Powering AV
AIN_
+5V
1µF
0.1µF
DD
10Ω
0.1µF
and DV
DV
DD
REF
AV
AIN_
DD
DD
power supply. Bypass an
DD
MAX1067
MAX1068
from a Single Supply
GND
DGND
AGND
AGND
SCLK
DOUT
CS
DOUT
CS
SCLK

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