MAX1068BEEG Maxim Integrated, MAX1068BEEG Datasheet - Page 24

• Manufacturer Part Number: MAX1068BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1068BEEG

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total harmonic
distortion of the MAX1067/MAX1068 at the frequencies of
interest (THD = -98db at 1kHz). If the chosen amplifier
has insufficient common-mode rejection, which results in
degraded THD performance, use the inverting configura-
tion (positive input grounded) to eliminate errors from this
source. Low-temperature-coefficient, gain-setting resis-
tors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use amplifier circuits with suf-
ficient loop gain at the frequencies of interest..
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1067/MAX1068s’ offset (±10mV
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Figure 20a. SPI Connections
Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
24
DOUT*
SCLK
CS
______________________________________________________________________________________
*WHEN CS IS HIGH, DOUT = HIGH-Z
0
SPI
1
MISO
SCK
I/O
SS
0
0
V
DD
1ST BYTE READ
0
4
0
CS
SCLK
DOUT
D5
MAX1067
MAX1068
0
6
DC Accuracy
D4
0
Distortion
0
D3
8
3RD BYTE READ
D2
20
D1
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required tempera-
ture range.
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1067/MAX1068 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 14-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream con-
tains D5 through D0 followed by S1 and S0.
Figure 20b. MICROWIRE Connections
LSB
D0
MSB
D13
S1
MICROWIRE
D12
S0
24
D11
I/O
SK
SI
HIGH-Z
SPI and MICROWIRE Interfaces
D10
2ND BYTE READ
12
D9
D8
Serial Interfaces
CS
SCLK
DOUT
D7
MAX1067
MAX1068
D6
16
D5