MAX1137EUA Maxim Integrated, MAX1137EUA Datasheet - Page 11

• Manufacturer Part Number: MAX1137EUA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1137EUA

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-8
• Maximum Power Dissipation: 362 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V

swing from (GND - 0.3V) to (V
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above V
The SGL/DIF of the configuration byte configures the
MAX1136–MAX1139 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF = 0) the
digital conversion results are the difference between the
“+” and the “-” analog inputs selected by CS[3:0] (Table 4).
When operating in differential mode, the BIP/UNI bit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
input in unipolar mode will cause the digital output
code to be zero. Selecting bipolar mode sets the differ-
ential input range to ±V
binary in unipolar mode and two’s complement in bipo-
lar mode, see the Transfer Functions section.
In single-ended mode the MAX1136–MAX1139 will
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
The MAX1136–MAX1139 feature a 2-wire interface con-
sisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1136–MAX1139 and the master at
rates up to 1.7MHz. The MAX1136–MAX1139 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit ). Series resistors (R
They protect the input architecture of the MAX1136–
MAX1139 from high voltage spikes on the bus lines, min-
imize crosstalk, and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. A minimum of eighteen clock cycles are required
to transfer the data in or out of the MAX1136–MAX1139.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
DD
.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
Single-Ended/Differential Input
______________________________________________________________________________________
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
REF
. A negative differential analog
REF
2-Wire Digital Interface
/2. The digital output code is
DD
+ 0.3V) without caus-
Unipolar/Bipolar
S
) are optional.
Bit Transfer
REF
.
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see HS-mode).
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1136–MAX1139 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiv-
er allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer the bus master should reattempt
communication at a later time.
Figure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
SDA
SCL
SDA
SCL
S
S
1
START and STOP Conditions
2
Sr
NOT ACKNOWLEDGE
Acknowledge Bits
ACKNOWLEDGE
8
P
9
11