MAX1137EUA Maxim Integrated, MAX1137EUA Datasheet - Page 16

• Manufacturer Part Number: MAX1137EUA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1137EUA

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-8
• Maximum Power Dissipation: 362 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V

The device memory contains all of the conversion
results when the MAX1136–MAX1139 release SCL. The
converted results are read back in a first-in-first-out
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF will be
excluded from a multichannel scan. The memory con-
tents can be read continuously. If reading continues
past the result stored in memory, the pointer will wrap
around and point to the first result. Note that only the
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Figure 10. Internal Clock Mode Read Cycles
Figure 11. External Clock Mode Read Cycle
16
A. SINGLE CONVERSION WITH INTERNAL CLOCK
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
S
1
S
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE ADDRESS
1
S
1
S
______________________________________________________________________________________
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
SLAVE ADDRESS
SLAVE ADDRESS
7
t
ACQ
7
MASTER TO SLAVE
SLAVE TO MASTER
t
ACQ1
7
7
1 1
R
1 1
R
A
A
CLOCK STRETCH
1 1
R
1 1
R
A
A
t
CONV
t
CONV1
t
t
ACQ
ACQ1
RESULT 1 (2 MSBs)
CLOCK STRETCH
RESULT (2 MSBs)
8
8
RESULT 2 MSBs
t
ACQ2
t
CONV2
8
1
A
1
A
t
CONV
t
CONV1
A
RESULT 2 (8 LSBs)
RESULT (8 LSBs)
CLOCK STRETCH
RESULT 8 LSBs
8
8
t
t
ACQN
CONVN
8
RESULT 1 ( 2MSBs)
1
A
1
A
1
A
t
ACQ2
P or Sr
P OR Sr
8
1
1
current conversion results will be read from memory.
The device must be addressed with a read command
to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
1
A
NUMBER OF BITS
t
RESULT N (2 MSBs)
ACQN
RESULT 1 (8 LSBs) A
NUMBER OF BITS
8
8
1
1
A
t
RESULT N (8MSBs)
CONVN
RESULT N (8 LSBs)
8
8
1
A
RESULT N (8LSBs)
1
A
8
P OR Sr
1
1
A
P or Sr
1
NUMBER OF BITS
NUMBER OF BITS