MAX1304ECM-T Maxim Integrated, MAX1304ECM-T Datasheet - Page 5

• Manufacturer Part Number: MAX1304ECM-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1304ECM-T

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 1075 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 71 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-48
• Maximum Power Dissipation: 1818.2 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
C
lar devices), f
unless otherwise noted. Typical values are at T
Digital Supply Current
(C
Shutdown Current
(Note 8)
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS (Figure 1)
Time to First Conversion Result
Time to Subsequent Conversions
CONVST Pulse-Width Low
(Acquisition Time)
CS Pulse Width
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR
WR to CS
CS to RD
RD to CS
Data Access Time
(RD Low to Valid Data)
Bus Relinquish Time (RD High)
CLK Rise to EOC Delay
CLK Rise to EOLC Fall Delay
CONVST Fall to EOLC Rise Delay
EOC Pulse Width
REF-
AVDD
LOAD
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
= 0.1µF, C
= +5V, V
= 100pF) (Note 7)
PARAMETER
CLK
DVDD
REF+-to-REF-
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
_______________________________________________________________________________________
= +3V, V
= 2.2µF || 0.1µF, C
AGND
= V
t
SYMBOL
CVEOLCD
t
DGND
I
I
t
t
EOLCD
I
PSRR
t
DVDD
DVDD
CONV
t
t
t
t
t
t
EOCD
t
AVDD
t
t
t
t
NEXT
ACQ
RDH
WRL
CTW
WTC
ACC
EOC
t
RDL
CTR
RTC
REQ
CS
A
= 0V, V
COM
= +25°C. See Figures 3 and 4.)
MAX1304/MAX1305/MAX1306,
all channels selected
MAX1308/MAX1309/MAX1310,
all channels selected
MAX1312/MAX1313/MAX1314,
all channels selected
SHDN = DVDD, V
SHDN = DVDD, RD = WR = high
V
Internal clock, Figure 7
External clock, Figure 8
Internal clock, Figure 7
External clock, Figure 8
(Note 9) Figures 6–10
Figure 6
Figures 7, 8, 9
Figures 7, 8, 9
Figure 6
Figure 6
Figure 6
Figures 7, 8, 9
Figures 7, 8, 9
Figures 7, 8, 9
Figures 7, 8, 9
Figure 8
Figure 8
Figures 7, 8, 9
Internal clock, Figure 7
External clock, Figure 8
AVDD
= 2.2µF || 0.1µF, C
REF
= +4.75V to +5.25V
= V
REFMS
CONDITIONS
CH
= +2.5V (external reference), C
MSV
= open
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
MIN
0.1
30
30
30
30
50
5
REF
(Note 10)
(Note 10)
(Note 10)
(Note 10)
= C
TYP
0.02
800
200
1.3
1.3
1.3
0.6
50
12
20
20
20
3
1
REFMS
A
1000.0
= 0.1µF, C
MAX
= T
900
225
2.6
2.6
2.6
10
30
30
1
MIN
to T
Cycles
Cycles
UNITS
Cycle
CLK
CLK
CLK
REF+
mA
dB
µA
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
5
=
,