STM32F372VCT6 STMicroelectronics, STM32F372VCT6 Datasheet - Page 16

• Manufacturer Part Number: STM32F372VCT6
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex M4 72MHz 256kB MCU FPU
• Manufacturer: STMicroelectronics

Specifications of STM32F372VCT6

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M4F
• Processor Series: STM32F372xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 1
• Interface Type: CAN, I2C, SPI, USART, USB
• Length: 14 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 84
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

Functional overview
3.10
3.11
3.11.1
3.11.2
16/128
Do not reconfigure GPIO pins which are not present on 48 and 64 pin packages to the
analog mode. Additional current consumption in the range of tens of µA per pin can be
observed if V
Direct memory access (DMA)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC,
SDADCs, general-purpose timers.
Interrupts and events
Nested vectored interrupt controller (NVIC)
The STM32F37x devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 60 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
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The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 29 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 84
GPIOs can be connected to the 16 external interrupt lines.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
DDA
is higher than V
Doc ID 022691 Rev 3
DDIO
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STM32F37x