AT89LP51ED2-20AAU Atmel, AT89LP51ED2-20AAU Datasheet - Page 147

• Manufacturer Part Number: AT89LP51ED2-20AAU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AAU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

19.6.1
3714A–MICRO–7/11
Master Transmitter Mode
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In
in the circles show the status code held in SSCS. At these points, actions must be taken by the
application to continue or complete the TWI transfer. The TWI transfer is suspended until the SI
flag is cleared by software.
When the SI flag is set, the status code in SSCS is used to determine the appropriate software
action. For each status code, the required software action and details of the following serial
transfer are given in
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver. In
order to enter a Master mode, a START condition must be transmitted. The format of the follow-
ing address packet determines whether Master Transmitter or Master Receiver mode is to be
entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is
entered.
A START condition is sent by writing the following value to SSCON:
SSIE must be set to enable the Two-wire Serial Interface, STA must be written to one to transmit
a START condition and SI must be cleared. The TWI will then test the Two-wire Serial Bus and
generate a START condition as soon as the bus becomes free. After a START condition has
been transmitted, the SI flag is set by hardware, and the status code in SSCS will be 08h (see
Table
SLA+W to SSDAT. Thereafter the SI bit should be cleared to continue the transfer.
When SLA+W has been transmitted and an acknowledgment bit has been received, SI is set
again and a number of status codes in SSCS are possible. Possible status codes in Master
mode are 18h, 20h, or 38h. The appropriate action to be taken for each of these status codes is
detailed in
After SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to SSDAT. SSDAT must only be written when SI is high. If not, the
access will be discarded and the previous value will be transmitted. After updating SSDAT, the
SI bit should be cleared to continue the transfer. This scheme is repeated until the last byte has
been sent and the transfer is ended by generating a STOP condition or a repeated START con-
dition. A STOP condition is generated by writing the following value to SSCON:
SSCON
Value
Figure 19-11
19-6). In order to enter MT mode, SLA+W must be transmitted. This is done by writing
Table
bit rate
CR2
to
19-6.
Figure
Table 19-6
SSIE
1
19-14, circles are used to indicate that the SI flag is set. The numbers
AT89LP51RD2/ED2/ID2 Preliminary
to
STA
1
Table
19-9.
STO
0
SI
0
AA
X
bit rate
CR1
bit rate
CR0
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