AT89LP51ED2-20AAU Atmel, AT89LP51ED2-20AAU Datasheet - Page 16

• Manufacturer Part Number: AT89LP51ED2-20AAU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AAU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

3.1.2
3.2
3.2.1
3.2.2
3.2.3
16
Internal Data Memory
AT89LP51RD2/ED2/ID2 Preliminary
SIG
DATA
IDATA
SFR
In addition to the 64K code space, the AT89LP51RD2/ED2/ID2 also supports a 512-byte User
Signature Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The
Atmel Signature Array is initialized with the Device ID in the factory. The User Signature Array is
available for user identification codes or constant parameter data. Data stored in the signature
array is not secure. Security bits will disable writes to the array; however, reads by an external
device programmer are always allowed. The signatures can be accessed with the Flash API
functions or low-level IAP interface. See
page 192
The AT89LP51RD2/ED2/ID2 contains 256 bytes of general SRAM data memory plus 128 bytes
of I/O memory mapped into a single 8-bit address space. Access to the internal data memory
does not require any configuration. The internal data memory has three address spaces: DATA,
IDATA and SFR; as shown in
mented internally. See
Figure 3-5.
The first 128 bytes of RAM are directly addressable by an 8-bit address (00H–7FH) included in
the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers
each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc-
tions using register addressing will only access the currently specified bank. The lower 128 bit
addresses are also mapped into DATA addresses 20H—2FH.
The full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1.
The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the
IDATA space.
The upper 128 direct addresses (80H–FFH) access the I/O registers. I/O registers on AT89LP
devices are referred to as Special Function Registers. The SFRs can only be accessed through
direct addressing. All SFR locations are not implemented. See
SFRs.
for more information.
LOWER
UPPER
128
128
Internal Data Memory Map
FFH
7FH
80H
0
“External Data Memory”
AND INDIRECT
ADDRESSING
ADDRESSING
ACCESSIBLE
BY INDIRECT
ACCESSIBLE
DATA/IDATA
BY DIRECT
IDATA
ONLY
Figure
3-5. Some portions of external data memory are also imple-
Section 24.4 “In-Application Programming (IAP)” on
ADDRESSING
ACCESSIBLE
BY DIRECT
below for more information.
SFR
SPECIAL
FUNCTION
REGISTERS
FFH
80H
Section 4.
PORTS
STATUS AND
CONTROL BITS
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)
TIMERS
for a listed of available
3714A–MICRO–7/11