AT89LP51ED2-20AAU Atmel, AT89LP51ED2-20AAU Datasheet - Page 182

• Manufacturer Part Number: AT89LP51ED2-20AAU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AAU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

22.1.7
22.1.8
182
Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected.
Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address
Operation: LSL
Operation: MOVC
Encoding:
Encoding:
AT89LP51RD2/ED2/ID2 Preliminary
Function: Shift MAC Accumulator Left Logically
Function: Move code byte relative to Alternate Data Pointer
LSL M
MOVC A, @A+/DPTR
Example: The M register holds the value 0C5B1A29384H. The following instruction,
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the
Cycles: 2
Cycles: 4
Bytes: 2
Bytes: 2
LSL M
leaves the M register holding the value 8B63452708H.
(M
(M
of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of the
unselected Data Pointer. The base register is not altered. Sixteen-bit addition is performed so a carry-out from
the low-order eight bits may propagate through higher-order bits. No flags are affected.
Accumulator to one of four values defined by the DB (define byte) directive.
TABLE:
If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator.
IF (DPS) = 0
THEN
ELSE
n+1
0
) ← 0
A5
A5
MOV
MOVC
RET
(A) ← ( (A) + (DPTR1) )
(A) ← ( (A) + (DPTR0) )
) ← (M
DB
DB
DB
DB
n
) n = 0 - 38
66H
/DPTR, #TABLE
A, @A+PC
77H
88H
99H
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
1
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