MAX1323ECM-T Maxim Integrated, MAX1323ECM-T Datasheet - Page 13

• Manufacturer Part Number: MAX1323ECM-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

To start a conversion using external clock mode, pull
CONVST low for at least the acquisition time (t
T/H acquires the signal while CONVST is low, and con-
version begins on the rising edge of CONVST. Apply an
external clock to the CLK pin. To avoid T/H droop
degrading the sampled analog input signals, the first
clock pulse should occur within 10µs from the rising
edge of CONVST, and have a minimum clock frequency
of 100kHz. The conversion result is available for read on
the rising edge of the 17th clock cycle (Figure 4).
In both internal and external clock modes, CONVST
must be held high until the last conversion result is
read. For best operation, the rising edge of CONVST
must be a clean, high-speed, low-jitter digital signal.
It is necessary to have a period of inactivity on the digi-
tal bus during signal aquisition. t
between the RD rising edge and the falling edge of
CONVST shown in Figure 4. Allow a minimum of 50ns
for t
Figures 3 and 4 show the interface signals for initiating
a read operation during a conversion cycle. CS can be
Figure 4. Reading a Conversion—External Clock
QUIET
.
CONVST
D0–D13
EOC
CLK
RD
CS
Reading a Conversion Result
______________________________________________________________________________________
Reading During a Conversion
TRACK
t
ACQ
t
19
SAMPLE
QUIET
1
14-Bit, Parallel-Interface ADCs
is the period
ACQ
t
17
2
t
). The
18
3
526ksps, Single-Channel,
t
13
low at all times; it can be low during the RD cycles, or it
can be the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC or EOLC to go low (about 1.6µs in internal
clock mode or 17 clock cycles in external clock mode)
before reading the first conversion result. Read the
conversion result by bringing RD low and latching the
data to the parallel digital-output bus. Bring RD high to
release the digital bus.
After applying power, allow the 1.0ms wake-up time to
elapse before initiating the first conversion. If using an
external clock, apply 20 clock pulses to CLK with
CONVST high before initiating the first conversion. If
using an internal clock, hold CONVST high for at least
2.0µs after the wake-up time is complete.
The internal reference circuits provide for analog input
voltages of 0 to +5V unipolar (MAX1319), ±5V bipolar
(MAX1323) or ±10V bipolar (MAX1327). Install external
capacitors for reference stability, as indicated in Table 1,
and as shown in the Typical Operating Circuits.
16
t
16
t
10
t
8
17
t
11
t
3
HOLD
t
t
12
2
t
20
18
t
9
19
t
QUIET
TRACK
20
SAMPLE
Power-Up Reset
Internal Reference
1
Reference
13