MAX1323ECM-T Maxim Integrated, MAX1323ECM-T Datasheet - Page 5

• Manufacturer Part Number: MAX1323ECM-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

TIMING CHARACTERISTICS (Figures 3, 4, 5, and 6) (Tables 1, 2)
Note 1: For the MAX1319, V
Note 2: INL is defined as the deviation of the analog value at any code from its theoretical value after offset and gain errors have
Note 3: Offset nulled.
Note 4: CONVST must remain low for at least the acquisition period.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Note 6: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
Note 7: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the rising
Conversion Time
CONVST Pulse-Width Low
(Acquisition Time)
CS Pulse Width
RD Pulse-Width Low
CS to RD Setup Time
RD to CS Hold Time
Data Access Time
(RD Low to Valid Data)
Bus Relinquish Time (RD High)
EOC Pulse Width
External CLK Period
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
EOC Low to RD
been removed.
to the falling edge of EOLC to a maximum of 0.25ms.
edge of CONVST and have a minimum clock frequency of 100kHz.
PARAMETER
_______________________________________________________________________________________
IN
= 0 to +5V. For the MAX1323, V
SYMBOL
t
CONV
t
ACQ
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
16
17
18
19
20
2
3
8
9
14-Bit, Parallel-Interface ADCs
Internal clock
External clock (Figure 4)
(Note 4)
Internal clock
External clock (Figure 4)
Logic sensitive to rising edges
Logic sensitive to rising edges
(Note 6)
(Note 7)
IN
526ksps, Single-Channel,
CONDITIONS
= -5V to +5V. For the MAX1327, V
0.16
MIN
0.1
30
30
80
90
20
20
20
0
0
0
IN
= -10V to +10V.
TYP
1.6
16
10
1
MAX
12.5
100
1.8
30
30
UNITS
cycles
Clock
Clock
cycle
MHz
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
5