M95M01-DFMN6TP STMicroelectronics, M95M01-DFMN6TP Datasheet - Page 24

• Manufacturer Part Number: M95M01-DFMN6TP
• Description: EEPROM 1Mb SPI bus EEPROM 256kB 16MHz
• Manufacturer: STMicroelectronics

Specifications of M95M01-DFMN6TP

• Rohs: yes

Instructions
Note:
Figure 14. Page Write (WRITE) sequence
24/45
The instruction is not accepted, and is not executed, under the following conditions:
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
S
C
D
S
C
D
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
7
0
6
1
5
Data byte 2
2
4
Instruction
3
3
4
2
W
5
1
is internally executed as a sequence of two consecutive
6
Doc ID 13264 Rev 11
0
7
7
23
8
6
22 21
9 10
5
Data byte 3
24-bit address
4
3
3
28 29 30 31 32 33 34 35
2
2
1
1
0
0
7
6
6
5
Data byte N
5
Data byte 1
4
4
3
3
36 37 38
2
2
M95M01-DF M95M01-R
1
1
0
0
39
MS30906V1