M95M01-DFMN6TP STMicroelectronics, M95M01-DFMN6TP Datasheet - Page 29

• Manufacturer Part Number: M95M01-DFMN6TP
• Description: EEPROM 1Mb SPI bus EEPROM 256kB 16MHz
• Manufacturer: STMicroelectronics

Specifications of M95M01-DFMN6TP

• Rohs: yes

M95M01-DF M95M01-R
6.10
Lock ID (available only in M95M01-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t
parameters). The instruction sequence is shown in
The instruction is discarded, and is not executed, under the following conditions:
Figure 18. Lock ID sequence
S
C
D
Q
If a Write cycle is already in progress,
If the Block Protect bits (BP1,BP0) = (1,1),
If a rising edge on Chip Select (S) happens outside of a byte boundary.
0
1
High impedance
2
Instruction
W
3
(as specified in AC characteristics in
4
Doc ID 13264 Rev 11
5
6
7
23
8
22 21
9 10
24-bit address
3
28 29 30 31 32 33 34 35
Figure
2
1
18.
0
7
Section 9: DC and AC
6
5
Data byte
4
3
36 37 38
2
Instructions
1
0
39
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