LFE3-150EA-7LFN1156C Lattice, LFE3-150EA-7LFN1156C Datasheet - Page 72

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LFE3-150EA-7LFN1156C

Manufacturer Part Number
LFE3-150EA-7LFN1156C
Description
FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet

Specifications of LFE3-150EA-7LFN1156C

Rohs
yes
Factory Pack Quantity
24

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE3-150EA-7LFN1156C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
LatticeECP3 External Switching Characteristics (Continued)
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Pin for Clock
Input
Left and Right Sides
t
t
f
t
t
f
t
t
f
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)
Left and Right Side Using DLLCLKIN Pin for Clock Input
t
t
f
t
t
f
t
t
f
t
t
f
Top Side Using PCLK Pin for Clock Input
t
t
f
t
t
f
t
t
f
t
t
f
DVECLKGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
Parameter
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Description
Over Recommended Commercial Operating Conditions
All ECP3EA Devices 0.775
All ECP3EA Devices
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
Device
3-19
0.775
0.775
0.790
0.775
0.775
0.790
Min. Max. Min. Max. Min. Max. Min. Max.
321
321
321
321
335
335
-9
0.225
0.225
0.210
0.225
0.225
0.210
250
405
405
405
460
460
460
235
235
235
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
0.775
0.775
0.775
0.790
0.790
0.775
0.775
0.790
0.790
321
321
321
321
335
335
335
335
-8
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
250
405
405
405
405
460
460
460
460
235
235
235
235
0.775
0.775
0.775
0.790
0.790
0.775
0.775
0.790
0.790
403
403
403
403
425
425
425
425
1, 2
-7
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
250
325
325
325
325
385
385
385
385
170
170
170
170
0.775
0.775
0.775
0.790
0.790
0.775
0.775
0.790
0.790
471
471
535
535
535
535
535
535
-6
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
250
280
250
250
250
345
311
311
311
130
130
130
130
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
ps
ps
ps
ps
ps
ps
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI

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