SST25VF032B-50-4C-S2AF Microchip Technology, SST25VF032B-50-4C-S2AF Datasheet - Page 11

• Manufacturer Part Number: SST25VF032B-50-4C-S2AF
• Description: Flash 32Mbit 50MHz
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-50-4C-S2AF

• Product Category: Flash
• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Organization: 4 KB x 1024

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©2011 Silicon Storage Technology, Inc.
High-Speed-Read (80 MHz)
Byte-Program
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will automatically increment until the highest memory
address is reached. Once the highest memory address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space. For example, once the data from address
location 3FFFFFH has been read, the next output will be from address location 000000H.
Figure 6: High-Speed-Read Sequence
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8
SCK
CE#
SO
SI
0B
MODE 3
MODE 0
HIGH IMPEDANCE
0 1 2 3 4 5 6 7 8
ADD.
15 16
11
23
-A
02
ADD.
0
] and a dummy byte. CE# must remain active low for the
23 24
ADD.
31 32
ADD.
32 Mbit SPI Serial Flash
HIGH IMPEDANCE
X
15 16
39 40
23
D
-A
MSB
ADD.
OUT
N
0
]. Following the address, the data is
23 24
47 48
D
ADD.
N+1
OUT
55 56
31 32
MSB LSB
SST25VF032B
BP
D
N+2
OUT
D
for the completion of
IN
63 64
1327 F08.0
39
D
S71327-04-000
N+3
OUT
71 72
Data Sheet
D
N+4
OUT
1327 F07.1
78
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