SST25VF032B-50-4C-S2AF Microchip Technology, SST25VF032B-50-4C-S2AF Datasheet - Page 9

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SST25VF032B-50-4C-S2AF

Manufacturer Part Number
SST25VF032B-50-4C-S2AF
Description
Flash 32Mbit 50MHz
Manufacturer
Microchip Technology
Datasheet

Specifications of SST25VF032B-50-4C-S2AF

Product Category
Flash
Rohs
yes
Data Bus Width
1 bit
Memory Type
Flash
Memory Size
32 Mbit
Architecture
Sectored
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
15 mA
Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Organization
4 KB x 1024

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF032B-50-4C-S2AF
Manufacturer:
MICROCHIP
Quantity:
1 200
Part Number:
SST25VF032B-50-4C-S2AF
Manufacturer:
SST
Quantity:
20 000
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF032B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-
Enable (WREN) instruction must be executed prior any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The com-
plete list of instructions is provided in Table 5.
All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the ris-
ing edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction has been shifted in (except for
Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before
receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the
device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the
most significant bit (MSB) first.
Table 5: Device Operation Instructions (1 of 2)
Instruction
Read
High-Speed Read
4 KByte Sector-Erase
32 KByte Block-Erase
64 KByte Block-Erase
Chip-Erase
Byte-Program
AAI-Word-Program
RDSR
EWSR
WRSR
WREN
WRDI
RDID
JEDEC-ID
8
7
6
3
4
5
Description
Read Memory
Read Memory at
higher speed
Erase 4 KByte of
memory array
Erase 32KByte block
of memory array
Erase 64 KByte block
of memory array
Erase Full Memory
Array
To Program One
Data Byte
Auto Address Incre-
ment Programming
Read-Status-Regis-
ter
Enable-Write-Status-
Register
Write-Status-Regis-
ter
Write-Enable
Write-Disable
Read-ID
JEDEC ID read
9
Op Code Cycle
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H)
or
1100 0111b (C7H)
0000 0010b (02H)
1010 1101b (ADH)
0000 0101b (05H)
0101 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H)
or
1010 1011b (ABH)
1001 1111b (9FH)
32 Mbit SPI Serial Flash
1
Cycle(s)
Address
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
2
Cycle(s)
Dummy
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SST25VF032B
Cycle(s)
1 to 
1 to 
2 to 
1 to 
1 to 
3 to 
Data
0
0
0
0
1
0
1
0
0
S71327-04-000
Data Sheet
Frequency
Maximum
25 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
02/11

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