SST25VF032B-50-4C-S2AF Microchip Technology, SST25VF032B-50-4C-S2AF Datasheet - Page 6

• Manufacturer Part Number: SST25VF032B-50-4C-S2AF
• Description: Flash 32Mbit 50MHz
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-50-4C-S2AF

• Product Category: Flash
• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Organization: 4 KB x 1024

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Hold Operation
Write Protection
Write Protect Pin (WP#)
The HOLD# pin is used to pause a serial sequence using the SPI flash memory, but without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits from Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
V
If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing.
Figure 4: Hold Condition Waveform
SST25VF032B provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL)
in the status register provide Write protection to the memory array and the status register. See Table 4
for the Block-Protection description.
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is
disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
IH.
HOLD#
SCK
WP#
H
L
L
Active
BPL
X
1
0
6
Hold
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
32 Mbit SPI Serial Flash
Active
Hold
SST25VF032B
S71327-04-000
Active
Data Sheet
1327 F05.0
T2.0 1327
IL
02/11
or