MAX7325ATG Maxim Integrated, MAX7325ATG Datasheet - Page 10

• Manufacturer Part Number: MAX7325ATG
• Description: Interface - I/O Expanders
• Manufacturer: Maxim Integrated
• Series: MAX7325r

Specifications of MAX7325ATG

• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.71 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: TQFN-24 EP
• Power Dissipation: 761.9 mW

I
and 8 Open-Drain I/Os
The MAX7325 operates as a slave that sends and
receives data through an I
uses a serial-data line (SDA) and a serial-clock line (SCL)
to achieve bidirectional communication between mas-
ter(s) and slave(s). The master initiates all data transfers
to and from the MAX7325 and generates the SCL clock
that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
MAX7325
Figure 1. 2-Wire Serial Interface Timing Details
Figure 2. START and STOP Conditions
10
SDA
SCL
2
CONDITION
C Port Expander with 8 Push-Pull
START
SDA
SCL
S
t
HD,STA
START CONDITION
t
LOW
2
t
R
C interface. The interface
t
SU,DAT
t
HIGH
Serial Interface
t
Serial Addressing
F
t
HD,DAT
CONDITION
STOP
P
t
REPEATED START CONDITION
SU,STA
Each transmission consists of a START condition sent
by a master, followed by the MAX7325’s 7-bit slave
addresses plus R/W bits, 1 or more data bytes, and
finally a STOP condition (Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Figure 3. Bit Transfer
SDA
SCL
t
HD,STA
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
START and STOP Conditions
t
SU,STO
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
Maxim Integrated
START