ASI4UC-G1-SR-7 ZMDI, ASI4UC-G1-SR-7 Datasheet - Page 18

• Manufacturer Part Number: ASI4UC-G1-SR-7
• Description: Interface - Specialized ASI
• Manufacturer: ZMDI

Specifications of ASI4UC-G1-SR-7

• Product Category: Interface - Specialized
• Rohs: yes
• Product Type: Actuator Sensor Interface IC
• Operating Supply Voltage: 16 V to 33.1 V
• Supply Current: 6 mA
• Maximum Power Dissipation: 850 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 25 C

2.3.4.
An important feature of the ASI4U is the 8-bit wide data port that consists of a 4-bit wide input section and a 4-
bit wide output section. The input and output sections work independently from each other allowing a
maximum of 8 devices (4 input and 4 output devices) to be connected to the ASI4U. For special applications
(compatibility), the so called Multiplex Mode can be activated that limits the output activation to a certain time
frame. Thus, a 4-bit wide bi-directional data I/O Port can be realized by external connection of the
corresponding data input and output pins.
The data port is accompanied by the data strobe signal DSR. There is a defined phase relation between a
data output event, the input data sampling and the activation of the DSR signal. Thus, it can be used to trigger
external logic or a micro controller to process the received data or to provide new input data for the AS-i slave
response. See chapter 3.7 Data Port and DSR on page 35 for further details.
2.3.5.
By default the logic signal (HIGH / LOW) that is present at the data input pins during the input sampling phase
is transferred without modification to the send register, which is interfaced by the UART. By that, the signal
becomes directly part of the slave response.
Some applications work with inverted logic levels. To avoid additional external inverters, the input signal can
be inverted by the ASI4U before transferring it to the send register. The inversion of the input signals can
either be done bit selective or jointly for all data input pins. See chapter 3.7.2 Input Data Pre-Processing on
page 36.
2.3.6.
To prevent input signal bouncing from being transferred to the AS-i Master, the data input signals can be
digitally filtered. Filter times can be configured in 7 steps from 128µs up to 8.192ms. Additionally there is a so
called AS-i Cycle Mode available. If activated, the filter time is determined by the actual AS-i cycle time. For
more detailed information refer to chapter 3.7.2 Input Data Pre-Processing on page 36.
The filter function can be enabled bit selective. Activation of the filters is done jointly either by E²PROM
configuration or by the logic state of parameter port pin P2. See chapter 3.7.2 Input Data Pre-Processing on
page 36.
2.3.7.
The fixed data output driving feature is thought to ease board level design for similar products that do not
require the full data output port width. The user can select one or more bits from the data output port to be
driven by a distinct logic level instead by the data that was sent by the master. The distinct output data is
stored in the E²PROM and can be set during final module configuration. Thus it is possible to signal the actual
IC profile to some external circuitry and to allow reuse of certain board designs for different product
applications.
See chapter 3.7.3 Fixed Output Data Driving on page 38 for further details.
2.3.8.
AS-i Complete Specification V3.0 newly defines a synchronous data I/O feature that allows a number of
slaves in the network to switch their outputs at the same time and to have their inputs sampled jointly. This
feature is especially useful if more than 4-bit wide data is to be provided synchronously to an application.
The synchronization point was defined to the data exchange event of the slave with the lowest address in the
network. This definition relies on the cyclical slave polling with increasing slave addresses per cycle that is
one of the basic communication principles of AS-i. The IC always monitors the data communication and
detects the change from a higher to a lower slave address. If such a change was recognized, the IC assumes
that the slave with the lower address has the lowest address in the network.
There are some special procedures that become active during the start of synchronous I/O mode operation
and if more than three consecutive telegrams were sent to the same slave address. This is described in more
detail in chapter 3.7.4 Synchronous Data I/O Mode on page 38.
Data Sheet
January 30, 2012
ASI4U / ASI4U-E
Spec. 3.0 Com
Data Port Pins
Data Input Inversion
Synchronous Data I/O Mode
Data Input Filtering
Fixed Data Output Driving
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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