ASI4UC-G1-SR-7 ZMDI, ASI4UC-G1-SR-7 Datasheet - Page 51

• Manufacturer Part Number: ASI4UC-G1-SR-7
• Description: Interface - Specialized ASI
• Manufacturer: ZMDI

Specifications of ASI4UC-G1-SR-7

• Product Category: Interface - Specialized
• Rohs: yes
• Product Type: Actuator Sensor Interface IC
• Operating Supply Voltage: 16 V to 33.1 V
• Supply Current: 6 mA
• Maximum Power Dissipation: 850 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 25 C

Parity_error
End_bit_error
Length_error
If at least one of these errors occurs, the received telegram is treated invalid. In this case, the UART will not
generate a Receive Strobe signal, move to asynchronous state and wait for a pause at the AS-i line input.
After a pause was detected, the UART is ready to receive the next telegram.
Receive Strobe signals are generally used to validate the correctness of the received data. In Master- and
Monitor Mode the signals are visible at the Parameter Ports for further processing by external circuitry.
Corresponding Parameter Port configurations can be found at Table 17 on page 34.
In Slave Mode, a Master Receive Strobe starts the internal processing of a master request. If the UART was
in asynchronous state before the signal was generated, it changes to synchronous state thereafter. In case
the received slave address matches the stored address of the IC, the transmitter is turned on by the Receive
Strobe pulse, letting the output driver settles smoothly at the operation point.
Data Sheet
January 30, 2012
ASI4U / ASI4U-E
Spec. 3.0 Com
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
pliant Universal AS-I IC
In order to take the jitter effects into account, the timing tolerance specifications
differ slightly from the definitions of the AS-i Complete Specification.
The sum of all information bits in master requests or slave responses (excluding
start and end bits, including parity bit) must be even. Violation of this rule is detected
as Parity_error.
The pulse to be detected
polarity, where n = 13 (78 s) for a master request and n = 6 (36 s) for a slave
response. Violation of this rule shall be detected as an End_bit_error.
Note: This stop pulse shall finish a master request or slave response.
Telegram length supervision is processed as follows. If during the first bit time after
the end pulse of a master request (equivalent to the 15
slaves (during the first three bit times for not synchronized slaves, equivalent to the
Bit times 15 to 17) or during the first bit time after the end pulse of a slave response
(equivalent to the 8
Length_error is detected.
th
Bit time) a signal different from a pause is detected, a
(
n
*
6

s
)


. 1
. 0
500
875


s
s
after the start pulse shall be of positive
th
Bit time) for synchronized
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