RSENC-DBLK-XM-U4 Lattice, RSENC-DBLK-XM-U4 Datasheet
RSENC-DBLK-XM-U4
Specifications of RSENC-DBLK-XM-U4
Related parts for RSENC-DBLK-XM-U4
RSENC-DBLK-XM-U4 Summary of contents
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Dynamic Block Reed-Solomon Encoder User’s Guide August 2010 IPUG40_03.6 ...
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... LatticeECP ........................................................................................................................................... /EC28 LatticeECP2M ............................................................................................................................................ 28 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Related Information............................................................................................................................................. 29 Revision History .................................................................................................................................................. 29 Appendix A. Resource Utilization ....................................................................................................... 30 LatticeECP and LatticeEC FPGAs ...................................................................................................................... 30 Ordering Part Number................................................................................................................................ 30 LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 31 Ordering Part Number................................................................................................................................ 31 LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 32 Ordering Part Number................................................................................................................................ 32 LatticeECP3 FPGAs............................................................................................................................................ 32 Ordering Part Number................................................................................................................................ 32 LatticeXP FPGAs ................................................................................................................................................ 33 Ordering Part Number................................................................................................................................ 33 LatticeXP2 FPGAs .............................................................................................................................................. 33 Ordering Part Number................................................................................................................................ 33 LatticeSC and LatticeSCM FPGAs ...
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... Lattice's Dynamic Block Reed-Solomon Encoder IP core can be used for forward error correction in many terres- trial communication, space communication, data storage, and data retrieval systems. The encoder is compliant with several industrial standards including the more recent IEEE 802.16-2004. The Reed-Solomon Encoder IP core provides a customizable solution allowing forward error correction in other non-standard applications as well ...
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... Lattice Semiconductor Table 1-2. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-3. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP2 Devices Quick Facts FPGA Families Supported Core ...
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... Lattice Semiconductor Table 1-4. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP2M Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-5. Dynamic Block Reed-Solomon Encoder IP core for LatticeSC Devices Quick Facts FPGA Families Supported Core ...
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... Lattice Semiconductor Table 1-6. Dynamic Block Reed-Solomon Encoder IP core for LatticeSCM Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-7. Dynamic Block Reed-Solomon Encoder IP core for LatticeXP Devices Quick Facts FPGA Families Supported Core ...
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... Lattice Semiconductor Table 1-8. Dynamic Block Reed-Solomon Encoder IP core for LatticeXP2 Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-9. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP3 Devices Quick Facts FPGA Families Supported Core ...
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... Lattice Semiconductor • Selectable Reed-Solomon standards – OC-192 – DVB – CCSDS – ATSC – IEEE 802.16-2004 WirelessMAN-SCa/OFDM – IEEE 802.16-2004 WirelessMAN-SC • Fully synchronous • Registered input selection • Systematic encoder • Full handshaking capability • Dynamically variable block size • ...
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Figure 2-1 illustrates the operation of a systematic encoder. Figure 2-1. Reed-Solomon Encoder Block Diagram din rstn enable byp ibstart blocksize numchks General Description Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy in the ...
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... Lattice Semiconductor Field Polynomial The field polynomial is defined by its decimal value (f). The decimal value of a field polynomial is obtained by set- ting x=2 in the polynomial. For example, the polynomial x nomial can be specified as any prime polynomial with decimal value Generator Polynomial The generator polynomial determines the value of the check symbols. The generator polynomial can be defined by the parameters starting root (gstart) and root spacing (rootspace) ...
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... Lattice Semiconductor Remainder Array The Remainder array is a shift register array. It stores the remainder polynomial after the polynomial division. The remainder polynomial becomes the check symbols once all information symbols have been processed. The Remainder array shifts-in the data from the Adder array while the information symbols are processed. When all the information symbols have been processed, the polynomial multiplication stops and the contents of the Remainder array are output to dout ...
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... Lattice Semiconductor Table 2-2. Interface Signal Descriptions (Continued) Port Bits I/O For Variable Check Symbols or Punctured Check Symbols This signal is used for two functions. 1) When the parameter Variable check symbols is “Yes”, this port is used to provide the number of check symbols value. The width of this port is equal to ceil(log2(Max. number of ...
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... Lattice Semiconductor Figure 2-4 shows the timing (7,3) double pipelined encoder with byp asserted during the operation of the encoder. The handshake signals are identical to normal operation, but the output is shifted due to the extra bypass data. Figure 2-4. Timing (7,3) Double Pipelined Encoder with byp Asserted ...
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... Lattice Semiconductor Figure 2-6. Timing (7,3) Double Pipelined Encoder with ibstart Re-asserted clk rstn ibstart enable byp D00 din dout status rfi outvalid Figure 2-7 explains the timing (7,3) double pipelined encoder with variable block size and variable check symbols. The figure also shows the timing of the optional output ports outvalid, obstart, obend, rfi, rfib and ibend ...
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... Lattice Semiconductor Figure 2-7. Timing (7,3) Encoder with Variable Block Size and Variable Check Symbols clk rstn enable byp ibstart blocksize 7 numchks 4 din D00 D01 D02 dout status outvalid obstart obend rfi rfib ibend IPUG40_03.6, August 2010 7 4 D10 D11 D12 D00 ...
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The IPexpress™ tool is used to create IP and architectural modules in the Diamond and ispLEVER software. Refer to “IP Core Generation” on page 24 The Dynamic Block Reed-Solomon Encoder IP core GUI allows the user to create a custom ...
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... Lattice Semiconductor Reed-Solomon Encoder Configuration GUI Figure 3-1 shows the contents of the Reed-Solomon Encoder IP core Configuration GUI. Figure 3-1. Reed-Solomon Encoder IP core Configuration GUI Core Configuration This parameter selects between custom and pre-defined standard configurations. The Parameter Settings of the Standard Configurations table in the Dynamic Block Reed-Solomon Encoder User’s Guide defines the fixed param- eter values for different standard configurations ...
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... Lattice Semiconductor Check Symbols Variable Check Symbols Specifies whether the number of check symbols is variable through the input port. Number of Check Symbols This parameter specifies the maximum value for number of check symbols provided through the input port numchks. This parameter selection is available when Variable check symbols is checked. ...
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... Lattice Semiconductor obend Determines whether the output port obend (output block end) is present. Summary The Summary entry in Figure 3-1 put Latency for the Reed-Solomon Encoder IP core is defined as the number of clock cycles between the sampling of the first input data and the availability of the first data at the output port three clock cycles when the inputs are registered and two clock cycles otherwise ...
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... An IP license is required to enable full, unrestricted use of the Dynamic Block Reed-Solomon Encoder IP core in a complete, top-level design license that specifies the IP core and device family is required to enable full use of the core in Lattice devices. Instructions on how to obtain licenses for Lattice IP cores are given at: http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm Users may download and generate the IP core and fully evaluate the core through functional simulation and imple- mentation (synthesis, map, place and route) without an IP license ...
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... Lattice Semiconductor Figure 4-1. IPexpress Dialog Box (Diamond Version) Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. ...
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... Lattice Semiconductor Figure 4-2. Configuration Dialog Box (Diamond Version) IPexpress-Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3 ...
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... This file provides a module which instantiates the RS Encoder core. This file can be easily mod- <username>_top.[v,vhd] ified for the user's instance of the RS Encoder core. This file is located in the rsenc_eval/<username>/src/rtl/top/ directory. This file is created when GUI “Generate” button is pushed and generation is invoked. This file <username>_generate.tcl may be run from command line. < ...
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... The \rsenc_eval directory is created by IPexpress the first time the core is generated and updated each time the core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and regen- erated each time the core with the same file name is regenerated. A separate \< ...
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... To use this project file in ispLEVER: 1. Choose File > Open Project. 2. Browse to \<project_dir>\rsenc_eval\<username>\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple- mentation will be imported to the project. ...
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... To regenerate an IP core in ispLEVER the IPexpress tool, choose Tools > Regenerate IP/Module the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box ...
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... Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a. p.m. Pacific Time. • For USA & Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • ...
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... Previous Lattice releases. 4.0 Core version 4.0: Full support of IPexpress flow, including LatticeECP/EC, LatticeECP2, LatticeSC, and LatticeXP 4.1 Updated appendices and added support for the LatticeECP2M family. 4.2 Added support for LatticeXP2 FPGA family. Updated LatticeECP/EC appendix. Updated LatticeSC appendix. 4.3 Added support for LatticeECP3 FPGA family. ...
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... Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core target- ing LatticeEC/ECP devices is RSENC-DBLK-E2-U4. Table A-2. Parameter Settings of the Evaluation Packages Configuration Description ...
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... Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2S family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core target- ing LatticeECP2/S devices is RSENC-DBLK-P2-U4. IPUG40_03.6, August 2010 1 (default) 2 ...
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... Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core target- ing LatticeECP3 devices is RSENC-DBLK-P3-U4. IPUG40_03.6, August 2010 is derived from the parameter settings listed in 1 ...
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... Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core target- ing LatticeXP2 devices is RSENC-DBLK-X2-U4. IPUG40_03.6, August 2010 is derived from the parameter settings listed in 1 ...
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... Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSCM family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core target- ing LatticeSC/M devices is RSENC-DBLK-SC-U4. IPUG40_03.6, August 2010 is derived from the parameter settings listed in 1 ...