RSENC-DBLK-XM-U4 Lattice, RSENC-DBLK-XM-U4 Datasheet - Page 21

• Manufacturer Part Number: RSENC-DBLK-XM-U4
• Description: Encoders, Decoders, Multiplexers & Demultiplexers Dynamic Block Reed Solomon Encoder
• Manufacturer: Lattice

Specifications of RSENC-DBLK-XM-U4

• Factory Pack Quantity: 1

Chapter 4:
IP Core Generation
This chapter provides information on licensing the Dynamic Block Reed-Solomon Encoder IP core, generating the
core using the Diamond or ispLEVER software IPexpress tool, running functional simulation, and including the core
in a top-level design. The Lattice Dynamic Block Reed-Solomon Encoder IP core can be used in LatticeECP3,
LatticeECP2/M, LatticeECP, LatticeSC/M, LatticeXP, and LatticeXP2 device families.
Licensing the IP Core
An IP license is required to enable full, unrestricted use of the Dynamic Block Reed-Solomon Encoder IP core in a
complete, top-level design. An IP license that specifies the IP core and device family is required to enable full use
of the core in Lattice devices. Instructions on how to obtain licenses for Lattice IP cores are given at:
http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm
Users may download and generate the IP core and fully evaluate the core through functional simulation and imple-
mentation (synthesis, map, place and route) without an IP license. The Dynamic Block Reed-Solomon Encoder IP
core also supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP
core that operate in hardware for a limited time (approximately four hours) without requiring an IP license (see
“Instantiating the Core” on page 25
for further details). However, a license is required to enable timing simulation, to
open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hard-
ware evaluation timeout limitation.
Getting Started
The Dynamic Block Reed-Solomon Encoder IP core is available for download from the Lattice IP Server using the
IPexpress tool. The IP files are automatically installed using ispUPDATE technology in any customer-specified
directory. After the IP core has been installed, the IP core will be available in the IPexpress GUI dialog box shown in
Figure
4-1.
The IPexpress tool GUI dialog box for the Dynamic Block Reed-Solomon Encoder IP is shown in
Figure
4-1. To
generate a specific IP core configuration the user specifies:
• Project Path – Path to the directory where the generated IP files will be loaded.
• File Name – “username” designation given to the generated IP core and corresponding folders and files.
• (Diamond) Module Output – Verilog or VHDL.
• (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
• Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3,
etc.). Only families that support the particular IP core are listed.
• Part Name – Specific targeted part within the selected device family.
IPUG40_03.6, August 2010
21 Dynamic Block Reed-Solomon Encoder User’s Guide