72V36110L6PF IDT, 72V36110L6PF Datasheet
72V36110L6PF
Specifications of 72V36110L6PF
Related parts for 72V36110L6PF
72V36110L6PF Summary of contents
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... TDO IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... Each FIFO has a data input port (D which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. ...
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... There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read ...
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... During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory ...
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... RT being LOW. Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Zero Latency Retransmit Timing. The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x36/x18) and read TABLE 1 — ...
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... In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. Output Ready FF/IR In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the Full Flag/ O FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO Input Ready memory ...
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... Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW (1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port will select Asynchronous operation ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 ABSOLUTE MAXIMUM RATINGS Symbol Rating V (2) Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... SKEW2 NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 7-5ns and 15ns are available as a standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. ...
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... Clock to Asynchronous Programmable Almost-Empty Flag PAEA NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Parameters apply to the PBGA package only. ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for t = 10ns CLK Output Load for t = 6ns, 7.5ns CLK NOTE: 1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns. ...
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... This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK ...
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... FSEL0 & FSEL1. PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V36100/ 72V36110 have internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IDT72V36100 0 Number of ( Words in (n+1) to 32,768 FIFO 32,769 to (65,536-(m+1)) (65,536-m) to 65,535 65,536 NOTE: 1. See table 2 for values for n, m. TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE ...
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... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence 36-BIT FIFO ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 1st Parallel Offset Write/Read Cycle D/Q35 D/Q19 D/Q17 D/Q8 EMPTY OFFSET REGISTER (PAE 2nd Parallel Offset Write/Read Cycle D/Q35 D/Q19 D/Q17 D/Q8 FULL OFFSET REGISTER (PAF) ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 1st Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER (PAE 2nd Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER (PAE 3rd Parallel Offset Write/Read Cycle D/Q8 FULL OFFSET REGISTER (PAF ...
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... Starting with the Empty Offset Register LSB and finishing with the Full Offset Register MSB. For x9 output bus width, a total of six read cycles must be performed on the offset registers. See Figure 3, Programmable Flag Offset Programming Sequence. ...
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... LOW on REN to enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is 36-BIT FIFO ...
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... REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup ...
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... LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + t after the valid RCLK cycle. SKEW WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the write port has been selected, then WEN must be held active, (tied LOW). READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK ...
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... BUS-MATCHING (BM, IW, OW) The pins BM, IW and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate on the word/byte size boundary as defined by the selection of bus width ...
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... HIGH. 36-BIT FIFO TM In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO, where D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT 36-BIT FIFO TM D35-D27 D26-D18 ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT 36-BIT FIFO ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS BM, OW RSS BE t RSS RM t RSS PFM t RSS IP t RSS RT t RSS SEN EF/OR FF/IR PAE PAF, HF ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF 36-BIT FIFO RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RSR ...
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... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus SKEW1 of WCLK and the rising edge of RCLK is less than HIGH. 3. First data word latency = SKEW1 RCLK REF. Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) 36-BIT FIFO TM t CLK t CLKH t CLKL 2 t ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 36-BIT FIFO TM 29 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 36-BIT FIFO TM 30 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...
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... Retransmit setup is complete after OR returns LOW more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 LOW. ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...
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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked set LOW during MRS. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V36100 and for the IDT72V36110. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) 36-BIT FIFO ( ...
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... RCLK LD REN DATA IN OUTPUT REGISTER NOTES LOW. 2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits. Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes CLKL CLKL WCLK t t ENS ENH ...
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... NOTES PAF offset maximum FIFO Depth. In IDT Standard Mode 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT Mode 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. 3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. ...
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... REN NOTES IDT Standard mode maximum FIFO depth 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 FWFT mode maximum FIFO depth 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... REN Qn Last Word EF t SKEW WR t CYH t CYC NOTE LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) 36-BIT FIFO ENS ENH FFA t CYC 2 t REF t CYL ...
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... EFA Last Word in Output Register NOTE LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) 36-BIT FIFO WFF t CYC t CYH ...
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... CYH CYL FFA FF NOTES LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) 36-BIT FIFO ...
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... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 29. Block Diagram of 65,536 x 72 and 131,072 x 72 Width Expansion ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V36100 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72V36110, with an 36-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 JTCKR t JTCKF t JTCKL TCK TDI/ TMS TDO t JRSR TRST (1) t JRST NOTE: 1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. SYSTEM INTERFACE PARAMETERS ...
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... Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V36100/72V36110 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. TDO T ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 Input = TMS NOTE: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram. All state transitions within the TAP controller occur at the rising edge of the TCLK pulse ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V36100/72V36110, the Part Number field contains the ...
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... IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs ...
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... Com‘l & Ind’l, PBGA & TQFP Clock Cycle Time (t Speed in Nanoseconds Commercial, TQFP Only Com'l & Ind'l, TQFP Only Low Power ⎯ 3.3V SuperSync II™ FIFO 65,536 x 36 131,072 x 36 ⎯ 3.3V SuperSync II™ FIFO 6117 drw39 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK ...