72V36110L6PF IDT, 72V36110L6PF Datasheet - Page 13

• Manufacturer Part Number: 72V36110L6PF
• Description: FIFO 128Kx36 3.3V SUPER SYNC II FIFO
• Manufacturer: IDT

Specifications of 72V36110L6PF

• Part # Aliases: IDT72V36110L6PF

TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
4. As well as selecting parallel programming mode, one of the default values will
PROGRAMMING FLAG OFFSETS
72V36110 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
be loaded depending on the state of FSEL0 & FSEL1.
also be loaded depending on the state of FSEL0 & FSEL1.
Full and Empty Flag offset values are user programmable. The IDT72V36100/
LD
H
H
H
H
LD
L
L
L
L
H
L
IDT72V36100, 72V36110
FSEL1
FSEL1
H
H
H
H
L
L
L
L
X
X
FSEL0
FSEL0
H
H
H
H
L
L
L
L
X
X
Program Mode
Offsets n,m
Parallel
Serial
16,383
8,191
4,095
2,047
1,023
255
127
511
TM
36-BIT FIFO
(3)
(4)
13
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
the current offset values. Offset values can be read via the parallel output port
Q
not possible to read the offset values in serial fashion.
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.
0
-Qn, regardless of the programming mode selected (serial or parallel). It is
In addition to loading offset values into the FIFO, it is also possible to read
Figure 3, Programmable Flag Offset Programming Sequence, summaries
The offset registers may be programmed (and reprogrammed) any time after
The IDT72V36100/72V36110 can be configured during the Master Reset
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
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OCTOBER 22, 2008