72V36110L6PF IDT, 72V36110L6PF Datasheet - Page 43

• Manufacturer Part Number: 72V36110L6PF
• Description: FIFO 128Kx36 3.3V SUPER SYNC II FIFO
• Manufacturer: IDT

Specifications of 72V36110L6PF

• Part # Aliases: IDT72V36110L6PF

SYSTEM INTERFACE PARAMETERS
TRST
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. 50pf loading on external output signals.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Data Output Hold
Data Output
TDI/
TMS
TDO
Parameter
TCK
Data Input
(1)
t
JTCKF
Symbol Test Conditions
t
t
DOH
t
DO
t
t
DS
DH
JRST
(1)
(1)
t
t
JTCKL
t
rise=3ns
fall=3ns
t
t
JTCKR
JRSR
t
t
TCK
DS
Min.
10
10
0
t
-
DH
IDT72V36100
IDT72V36110
Figure 31. Standard JTAG Timing
t
JTCKH
Max. Units
20
-
TM
-
-
36-BIT FIFO
ns
ns
ns
43
(V
NOTE:
1. Guaranteed by design.
JTAG AC ELECTRICAL
CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
CC
= 3.3V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCK
JTCKH
JTCKL
JTCKR
JTCKF
JRST
JRSR
COMMERCIAL AND INDUSTRIAL
Conditions Min. Max. Units
Test
t
DO
-
-
-
-
-
-
-
TEMPERATURE RANGES
OCTOBER 22, 2008
100
40
40
50
50
-
-
TDO
5
5
-
-
-
-
-
(1)
(1)
6117 drw36
ns
ns
ns
ns
ns
ns
ns