W65C21S6TPG-14 Western Design Center (WDC), W65C21S6TPG-14 Datasheet - Page 15

• Manufacturer Part Number: W65C21S6TPG-14
• Description: Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
• Manufacturer: Western Design Center (WDC)

Specifications of W65C21S6TPG-14

• Rohs: yes
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Input Voltage Range (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10
• Supply Current (max): - 100 mA

A second output mode allows CA2 to be used in conjunction with CA1 to “handshake” between the
processor and the peripheral device. On the A side, this technique allows positive control of data
transfers from the peripheral device into the microprocessor. The CA1 input signals the processor that
data is available by interrupting the processor. The processor reads the data and sets CA2 low. This
signals the peripheral device that it can make new data available.
The final output mode can be selected by setting bit 4 of CRA to a 1. In this mode, CA2 is a simple
peripheral control output that can be set high or low by setting bit 3 of CRA to a 1 or a 0 respectively.
CB1 operates as an interrupt input only in the same manner as CA1. Bit 7 of CRB is set by the active
transition selected by bit 0 of CRB. Likewise, the CB2 input mode operates exactly the same as the CA2
input modes. The CB2 output modes, CRB bit 5=1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data into the Peripheral B Output Register. Also, the “handshaking”
operates on data transfers from the processor into the peripheral device.
INTERRUPT REQUEST (IRQAB, IRQBB)
The active low Interrupt Request lines (IRQAB and IRQBB) act to interrupt the microprocessor either
directly or through external interrupt priority circuitry. These lines are open drain and are capable of
sinking 3.2 milliamps from an external source. This permits all interrupt request lines to be tied together
in a wired OR configuration. The A and B in the titles of these lines correspond to the peripheral port B so
that each interrupt request line services one peripheral data port.
Each interrupt Request line has two interrupt flag bits that can cause the Interrupt Request line to go low.
These flags are bits 6 and 7 in the two Control Registers (CRA, CRB). These flags act as the link
between the peripheral interrupt signals and the microprocessor interrupt inputs.
Each flag has a
corresponding interrupt disable bit which allows the processor to enable or disable the interrupt from each
of the four interrupt inputs (CA1, CA2, CB1, CB2) The four interrupt flags are set (enabled) by active
transitions of the signal on the interrupt input (CA1, CA2, CB1, CB2).
CRA bit 7 (IRQA1) is always set an active transition of the CA1 interrupt input signal. However, IRQAB
can be disabled by setting bit 0 in CRA to a 0. Likewise, CRA bit 6 (IRQA2) can be set by an active
transition of the CA2 interrupt input signal and IRQAB can be disabled by setting bit 3 in CRA to a 0.
Both bit 6 and bit 7 in CRA are reset by a “Read Peripheral Output Register A” operation. This is defined
as an operation in which the read/write, proper data direction register and register select signals are
provided to allow the processor to read the Peripheral A I/O port. A summary of IRQA control is shown in
Table 3.
Control of IRQBB is performed in exactly the same manner as that described above for IRQAB. Bit 7 in
CRB (IRQB1) is set by an active transition on CB1 and IRQBB from this flag is controlled by CRB bit 0.
Likewise, bit 6 (IRQB2) in CRB is set by an active transition on CB2 and IRQBB from this flag is controlled
by CRB bit 3.
Also both bit 6 and bit 7 of CRB are reset by a “Read Peripheral B Output Register” operation. A
summary of IRQBB control is shown in Table 3.
INTERRUPT STATUS CONTROL LOGIC (ISCA, ISCB)
The four interrupt/peripheral control lines CA1, CA2, CB1, and CB2) are controlled by the Interrupt Status
Control logic (A, B).
This logic interprets the contents of the corresponding Control Register, thus
allowing these lines to perform various control functions as described in Figure 6.
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