W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet
W65C02S6TPG-14
Specifications of W65C02S6TPG-14
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W65C02S6TPG-14 Summary of contents
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October 19, 2010 8–bit Microprocessor WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. ...
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INTRODUCTION ....................................................................................................... 5 1.1 F W65C02S ........................................................................................................... 5 EATURES OF THE 2 FUNCTIONAL DESCRIPTION .................................................................................. 6 2 (IR) NSTRUCTION EGISTER 2 (TCU) ........................................................................................................... 6 IMING ONTROL NIT 2.3 ...
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DC, AC AND TIMING CHARACTERISTICS .......................................................... 23 6 -40°C HARACTERISTICS 6 -40°C HARACTERISTICS 7 CAVEATS ............................................................................................................... 30 8 HARD CORE MODEL ............................................................................................. 31 8.1 F ...
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TABLE 3-1 VECTOR LOCATIONS ............................................................................................................ 12 TABLE 3-2 PIN FUNCTION TABLE ......................................................................................................... 12 TABLE 4-1 ADDRESSING MODE TABLE ................................................................................................ 20 TABLE 5-1 INSTRUCTION SET TABLE ................................................................................................... 21 TABLE 5-2 W65C02S OPCODE MATRIX ................................................................................................. 22 TABLE 6-1 ABSOLUTE MAXIMUM RATINGS .......................................................................................... ...
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INTRODUCTION The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the PHI2 clock can be stopped when the high (logic 1) or low (logic 0) state. The ...
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FUNCTIONAL DESCRIPTION The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control Section. Instructions obtained from program memory are executed by implementing a series of data transfers within the Register Section. Signals ...
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Program Counter Register (PC) The 16-bit Program Counter Register (PC) provides the addresses which are used to step the microprocessor through sequential program instructions. instruction or operand is fetched from program memory. 2.8 Stack Pointer Register (S) The Stack ...
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Figure 2-2 W65C02S Microprocessor Programming Model 8 ...
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PIN FUNCTION DESCRIPTION 3.1 Address Bus (A0-A15) The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the Data Bus. The address lines can be set to the high impedance state by ...
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Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O) Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby Mode, PHI2 can be held in either ...
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Set Overflow (SOB) A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The signal is sampled on the rising edge of PHI2. SOB was originally intended for fast input ...
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Table 3-1 Vector Locations FFFE, F BRK/IRQB FFFC, D RESB FFFA, B NMIB Table 3-2 Pin Function Table Pin A0-A15 Address Bus BE Bus Enable D0-D7 Data Bus IRQB Interrupt Request MLB Memory Lock NC No Connection NMIB Non-Maskable Interrupt ...
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Figure 3-1 W65C02S 40 Pin PDIP Pinout Figure 3-2 W65C02S 44 Pin PLCC Pinout 13 ...
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Figure 3-3 W65C02S 44 Pin QFP Pinout 14 ...
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ADDRESSING MODES The W65C02S is capable of directly addressing 65,536 bytes of memory. The Program Address and Data Address space is contiguous throughout the 65,536 byte address space. Words, arrays, records, or any data structures may span the 65,536 ...
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Absolute Indexed with With the Absolute Indexed with Y addressing mode, the Y Index Register is added to the second and third bytes of the instruction to form the 16-bit effective address. Byte: Instruction: Operand address: ...
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Implied i Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction. Byte: Instruction: Operand address: 4.9 Program Counter Relative r The Program Counter relative addressing mode, sometimes referred to as Relative Addressing, is ...
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Zero Page Indexed Indirect (zp,x) The Zero Page Indexed Indirect addressing mode is often referred to as Indirect,X. The second byte of the instruction is the zero page address to which the X Index Register is added and the ...
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Zero Page Indirect Indexed with Y (zp), y The Zero Page Indirect Indexed with Y addressing mode is often referred to as Indirect Y. The second byte of the instruction points to the low byte of a two byte ...
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Table 4-1 Addressing Mode Table Address Mode 1. Absolute a 2. Absolute Indexed Indirect (a,x) 3. Absolute Indexed with X a,x 4. Absolute Indexed with Y a,y 5. Absolute Indirect (a) 6. Accumulator A 7. Immediate # 8. Implied i ...
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OPERATION TABLES 1. ADC ADd memory to accumulator with Carry AND "AND" memory with accumulator 2. Arithmetic Shift one bit Left, memory or 3. ASL accumulator •BBR Branch on Bit Reset 4. •BBS 5. Branch of Bit Set 6. ...
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MSD ORA BRK 0 (zp,x) a ORA ORA BPL 1 (zp) ∗ (zp),y r JSR AND 2 a (zp,x) AND AND BMI 3 (zp) ∗ zp,x • (zp),y r EOR RTI 4 (zp,x) s EOR BVC ...
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DC, AC AND TIMING CHARACTERISTICS Table 6-1 Absolute Maximum Ratings Supply Voltage Input Voltage Storage Temperature This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application ...
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DC Characteristics TA = -40°C to +85°C (PLCC, QFP) TA= 0°C to 70°C (DIP) Sy mbol VDD Supply Voltage Input High Voltage (1) Vih BE, D0-D7, RDY, SOB IRQB, NMIB, PHI2, RESB Input Low Voltage (1) Vil BE, D0-D7, ...
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AC Characteristics TA = -40°C to +85°C (PLCC, QFP) TA= 0°C to 70°C (DIP) Symbol Parameter VDD Supply Voltage tACC Access Time tAH Address Hold Time tADS Address Setup Time tBVD BE to Valid Data (1) CEXT Capacitive Load ...
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Figure 6-3 General Timing Diagram Timing Notes: 1. Timing measurement points are 50% VDD. 2. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for system time base and PHI2 ...
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Table 6-4 Operation, Operation Codes and Status Register Operation # Immediate Data ~ NOT → AND Exclusive ADC 6D 7D A+M+C→A AND 2D 3D A^M→A C← ...
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Operation # Immediate Data ~ NOT ^ AND Exclusive JSR Jump to Subroutine 20 M → A LDA → X LDX AE M → Y LDY → ...
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Operation # Immediate Data ~ NOT ^ AND Exclusive →M STY 8C 00 → M STZ → X TAX M → X TAY BC ~A∧M → M TRB IC ...
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CAVEATS Table 7-1 Microprocessor Operational Enhancements Function Indexed addressing across page boundary Execution of invalid OpCodes. Jump indirect, operand = XXFF. Read/Modify/Write instruction at effective address. Decimal flag. Flags after decimal operation. Interrupt after fetch of BRK instruction Ready. ...
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HARD CORE MODEL 8.1 Features of the W65C02S Hard Core Model • The W65C02S core uses the same instruction set as the W65C02S. • The only functional difference between the W65C02S and W65C02S core is the RDY pin. The ...
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ORDERING INFORMATION Description W65C = standard product Product Identification Number Foundry Process 6=.6u T= TSMC Foundry Package P = Plastic Dual-In-Line, 40 pins PL = Plastic Leaded Chip Carrier, 44 pins RoHS/Green Compliance G = RoHS/Green Compliant (Wafer and ...