W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet - Page 9

• Manufacturer Part Number: W65C02S6TPG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TPG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

3.1
The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on
the Data Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal.
3.2
The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers.
When Bus Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers
are set to the high impedance status. Bus Enable is an asynchronous signal.
3.3
The eight Data Bus lines D0-D7 are used to provide instructions, data and addresses to the
microprocessor and exchange data with memory and I/O registers. These lines may be set to the high
impedance state by the Bus Enable (BE) signal.
3.4
The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The
program counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable
(I) flag is set to a “1” disabling further interrupts before jumping to the interrupt handler. These values are
used to return the processor to its original state prior to the IRQB interrupt. The IRQB low level should be
held until the interrupt handler clears the interrupt request source. When Return from Interrupt (RTI) is
executed the (I) flag is restored and a new interrupt can be handled. If the (I) flag is cleared in an
interrupt handler, nested interrupts can occur. The Wait-for-Interrupt (WAI) instruction may be used to
reduce power and synchronize with, as an example timer interrupt requests.
3.5
The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in
a multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB
is low. Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and
TSB memory referencing instructions.
3.6
A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence after the
current instruction is completed. Since NMIB is an edge-sensitive input, an interrupt will occur if there is a
negative transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further
interrupts will occur if NMIB remains low. The NMIB signal going low causes the Program Counter (PC) and
Processor Status Register information to be pushed onto the stack before jumping to the interrupt handler.
These values are used to return the processor to its original state prior to the NMIB interrupt.
3.7
The No Connect (NC) pins are not connected internally and should not be connected externally.
3 PIN FUNCTION DESCRIPTION
Address Bus (A0-A15)
Bus Enable (BE)
Data Bus (D0-D7)
Interrupt Request (IRQB)
Memory Lock (MLB)
Non-Maskable Interrupt (NMIB)
No Connect (NC)
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