W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet - Page 24

• Manufacturer Part Number: W65C02S6TPG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TPG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

Sy
VDD
Vih
Vil
in
Iin
Ioh
Iol
Idd
Isby
Cin
Cts
mbol
6.2
Supply Voltage
Input High Voltage (1)
Input Low Voltage (1)
Input
VDD=max)
D0-D7 (off state)
Output High current (Voh=VDD-.4, VDD=min)
SYNC, VPB
Output Low current (Vol=0.4, VDD=min)
SYNC, VPB
Supply Current (with Tester Loading)
Supply Current (Core)
Standby Current Outputs Unloaded
*Capacitance (Vin=0V, TA=25°C, f-1MHz)
basis.
BE, D0-D7, RDY, SOB
IRQB, NMIB, PHI2, RESB
BE, D0-D7, RDY, SOB,
IRQB, NMIB, PHI2, RESB
BE, IRQB, NMIB, PHI2, RESB, SOB, RDY
A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB,
A0-A15, D0-D7, MLB, PHI1O, PHI2O, RDY, RWB,
BE, IRQB, NMIB, PHI2, SOB=VDD
BE, IRQB, NMIB, PHI2, RESB, RDY, SOB
A0-A15, D0-D7, RWB
*Not inspected during production test; verified on a sample
(1) For high speed tests, Vih and Vil are set for VDD-.2v and VSS+.2V. The input “1” and “0” thresholds are tested at 1 MHz.
Leakage
DC Characteristics TA = -40°C to +85°C (PLCC, QFP) TA= 0°C to 70°C (DIP)
Current
Figure 6-1 Idd vs Vdd
(Vin=0.4
to
2.4,
5.0 +/- 5%
Min
4.75
VDDx0.7
VDD-0.4
VSS-0.3
VSS-0.3
-20
-20
700
1.6
-
-
-
-
Table 6-2 DC Characteristics
Max
5.25
VDD+0.3
VDD+0.3
VDDx0.3
VSS+0.4
20
20
-
-
1.5
0.5
1
5
3.0
3.3 +/- 10%
Min
VDDx0.7
VDD-0.4
VSS-0.3
VSS-0.3
-20
-20
350
1.6
-
-
-
-
Max
3.6
VDD+0.
3
VDD+0.
3
VDDx0.
3
VSS+0.4
20
20
-
-
1.0
0.3
1
5
3.0 +/- 5%
Min
2.85
VDDx0.7
VDD-0.4
VSS-0.3
VSS-0.3
-20
-20
300
1.6
-
-
-
-
Figure 6-2 F Max vs Vdd
Max
3.15
VDD+0.3
VDD+0.3
VDDx0.3
VSS+0.4
20
20
-
-
1.0
0.25
1
5
2.5 +/- 5%
Min
2.37
VDDx0.7
VDD-0.4
VSS-0.3
VSS-0.3
-20
-20
200
1.0
-
-
-
-
Max
2.63
VDD+0.3
VDD+0.3
VDDx0.3
VSS+0.4
20
20
-
-
0.75
0.2
1
5
1.8 +/- 5%
Min
1.71
VDDx0.7
VDD-0.4
VSS-0.3
VSS-0.3
-20
-20
100
0.5
-
-
-
-
Max
1.89
VDD+0.3
VDD+0.3
VDDx0.3
VSS+0.1
20
20
-
-
0.5
0.15
1
5
24
Unit
s
V
V
V
nA
nA
uA
mA
MHz
uA
pF
mA/