W65C21N6TPLG-14 Western Design Center (WDC), W65C21N6TPLG-14 Datasheet

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W65C21N6TPLG-14

Manufacturer Part Number
W65C21N6TPLG-14
Description
Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
Manufacturer
Western Design Center (WDC)
Datasheet

Specifications of W65C21N6TPLG-14

Rohs
yes
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
PLCC-44
Input Voltage Range (max)
5.5 V
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
27
Supply Current (max)
- 0.4 mA
August 30, 2010
W65C21
(W65C21N and W65C21S)
Peripheral Interface Adapter (PIA)

Related parts for W65C21N6TPLG-14

W65C21N6TPLG-14 Summary of contents

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August 30, 2010 W65C21 (W65C21N and W65C21S) Peripheral Interface Adapter (PIA) ...

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WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made ...

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INTRODUCTION The WDC W65C21 (W65C21N and W65C21S very flexible Peripheral Interface Adapter (PIA) for use with WDC’s 65xx, 68xx, and other 8-bit microprocessor families. The W65C21 provides programmed microprocessor control two peripheral devices (Port A ...

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IRQAB CON TRO L REGISTER A (CRA ) DATA BUS D3 BUFFER OUTPUT BUS D4 (DBB ) D5 PERIPHERAL D6 OUTPUT D7 REGISTER A (ORA INPU T REG ISTER PERIPHERAL (DIR) OUTPUT REGISTER B (ORB ...

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ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Value Supply Voltage -0 Input Voltage V -0 Output Voltage V -0 OUT Operating Temp. - Range - Industrial Storage -55 to ...

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W65C21N DC CHARACTERISTICS (V = 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current CA1, CB1, CS0, CS1, CS2B, RESB, RS0, RS1, RWB , PHI2 Three-State (Off State), Leakage Current D0-D7, PB0-PB7, CB2 Input ...

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W65C21S DC CHARACTERISTICS (V = 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current CA1, CB1, CS0, CS1, CS2B, RESB, RS0, RS1, RWB , PHI2 Three-State (Off State), Leakage Current D0-D7, PB0-PB7, CB2 Input ...

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AC TIMING CHARACTERISTICS Parameter Symbol PHI2 Cycle t CYC PHI2 Pulse Width PHI2 Rise and Fall Time t rc READ TIMING Parameter Symbol Address Set-Up Time t ACR Address Hold Time t CAR Peripheral Data Setup Time t PCR Data ...

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PHI2 t ACW RS0, RS1, CS0, CS1, CS2B RWB t DCW D0-D7 DATA IN PA0-PA7 PB0-PB7 t CDR CB2 (PULSE OUT) CB1 CB2 (HANDSHAKE) Figure 5 Write Timing Waveforms t CYC CAW ...

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PHI2 t ACR RS0, RS1, CSO, CS1, CS2B t PCR PA0-PA7 PB0-PB7 t CDR D0-D7 DATA IN CA2 (PULSE OUT) CA1 CA2 (HANDSHAKE) CA1,CA2 CB1,CB2 IRQAB, IRQBB IRQAB, IRQBB t CYC CAR ...

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REGISTER SELECT PIN RS1 RS0 Figure 9A Port A, CA2 Buffers – W65C21N DDR DATA INPUT Figure 10A Port A, CA2 Buffers – W65C21S Table 1 Control Registers ...

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SIGNAL DESCRIPTION The PIA interfaces to the 65xx and 68xx microprocessor families with a reset line, a PHI2 clock line, a read/write line, two interrupt request lines, two register select lines, three chip select lines and an 8-bit bidirectional data ...

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PERIPHERAL DATA PORT B (PA0-PA7) Peripheral Data Port 8-line, bidirectional bus used for the transfer of data, control and status information between the W65C21 and a peripheral device. Functional operation is identical to Peripheral Data Port A, ...

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DATA DIRECTION REGISTERS (DDRA, DDRB) The Data Direction Registers (DDRA, DDRB) allow the processor to program each line in the 8-bit Peripheral I/O port to be either an input or an output. Each bit in DDRA controls the corresponding line ...

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A second output mode allows CA2 to be used in conjunction with CA1 to “handshake” between the processor and the peripheral device. On the A side, this technique allows positive control of data transfers from the peripheral device into the ...

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PERIPHERAL I/O PORTS (PA0-PA7, PB0-PB7) The Peripheral A and Peripheral B I/O ports allow the microprocessor to interface to the input lines on a peripheral device by writing data into the Peripheral Output Register. They also allow the processor to ...

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PERIPHERAL OUTPUT REGISTERS (ORA, ORB) All output data to a peripheral is stored in the corresponding Output Register (ORA or IRB). This data is then presented to the Peripheral Interface Buffer (A and B) and placed on the respective I/O ...

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CRA (CRB) ACTIVE TRANSITION OF BIT 1 BIT 0 INPUT SIGNAL Negative 0 1 Negative 1 0 Positive 1 1 Positive *Note: Bit 7 of CRA (CRB) will be set to a Logic active transition ...

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DIM MIN A 51.69 B 13.72 C 3.94 D 0.36 E 1.02 F 2.54 G 1.65 H 0.20 J 15. 0.51 M 2.92 Figure 9 Package Dimensions 40-Pin Plastic Dip ...

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... Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at conductive workstations. 3. Ground all assembly and repair tools. ORDERING INFORMATION W65C21N6TPLG-14 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 W65C 21N 6T ...

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