W65C21N6TPLG-14 Western Design Center (WDC), W65C21N6TPLG-14 Datasheet - Page 18

• Manufacturer Part Number: W65C21N6TPLG-14
• Description: Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
• Manufacturer: Western Design Center (WDC)

Specifications of W65C21N6TPLG-14

• Rohs: yes
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Input Voltage Range (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 27
• Supply Current (max): - 0.4 mA

*Note: Bit 6 of CRA (CRB) will be set to a Logic 1 by an active transition of the CA2 (CB2) signal.
This is independent of the state of bit 0 in CRA (CRB).
*Note: Bit 7 of CRA (CRB) will be set to a Logic 1 by an active transition of the CA1 (CB1) signal. This is independent of the state of bit
BIT 5
BIT 5
BIT 5
BIT 1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
CRA (CRB)
CRA (CRB)
CRA (CRB)
CRA (CRB)
BIT 4
BIT 4
BIT 4
0
0
1
1
0
0
1
1
0
0
1
1
BIT 0
0
1
0
1
BIT 3
BIT 3
BIT 3
0
1
0
1
0
1
0
1
0
1
0
1
ACTIVE TRANSITION OF
Table 3 Interrupt Input/Peripheral Control Line Operation.
INPUT SIGNAL*
“Handshake on Read”
“Handshake on Read”
ACTIVE TRANSITION OF
ACTIVE TRANSITION OF
ACTIVE TRANSITION OF
Negative
Negative
Positive
Positive
INPUT SIGNAL*
INPUT SIGNAL*
INPUT SIGNAL*
Manual Output
Manual Output
Manual Output
Manual Output
Pulse Output
Pulse Output
Negative
Negative
Positive
Positive
CA2/CB2 INPUT MODES
CA2 OUTPUT MODES
CB2 OUTPUT MODES
CA1/CB1 CONTROL
0 in CRA (CRB).
Disable – remains high
Enable – goes low when bit 7 in CRA (CRB) is set by active
transition of signal on CA1 (CB1)
Disable – remains high
Enable – as explained above
Disable – remains high
Enable – goes low when bit 6 in CRA (CRB) is set by
active transition of signal on CA2 (CB2)
Disable – remains high
Enable – as explained above
CA2 is set high on ac active transition of the CA1
interrupt input signal and set low by a microprocessor
“Read A Data” operation. This allows positive control of
data transfers from the peripheral device to the
microprocessor.
CA2 goes low for one cycle after a microprocessor
“Read A Data” operation. This pulse can be used to
signal the peripheral device that data was taken.
CA2 set low
CA2 set high
CB2 is set low on microprocessor “Write B Data” and is
set high by an active transition of the CB1 input signal.
This allows positive control of data transfers from the
microprocessor to the peripheral device.
CB2 goes low for one cycle after a microprocessor
“Write B Data” operation. This can be used to signal the
peripheral device that data is available.
CB2 set low
CB2 set high
IRQAB (IRQBB) INTERRUPT OUTPUTS
IRQAB (IRQBB) INTERRUPT OUTPUTS
IRQAB (IRQBB) INTERRUPT OUTPUTS
IRQAB (IRQBB) INTERRUPT OUTPUTS
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