W65C21N6TPLG-14 Western Design Center (WDC), W65C21N6TPLG-14 Datasheet - Page 13

• Manufacturer Part Number: W65C21N6TPLG-14
• Description: Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
• Manufacturer: Western Design Center (WDC)

Specifications of W65C21N6TPLG-14

• Rohs: yes
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Input Voltage Range (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 27
• Supply Current (max): - 0.4 mA

PERIPHERAL DATA PORT B (PA0-PA7)
Peripheral Data Port B is an 8-line, bidirectional bus used for the transfer of data, control and status
information between the W65C21 and a peripheral device. Functional operation is identical to Peripheral
Data Port A, thus allowing the W65C21 to independently control two peripheral devices.
READ/WRITE SIGNAL (RWB)
Read/Write (RWB) controls the direction of data transfers between the PIA and the data lines associated
with the CPU and the peripheral devices. A high on the RWB line permits the peripheral devices to
transfer data to the CPU from the PIA. A low on the RWB line allows data to be transferred from the CPU
to the peripheral devices from the PIA.
REGISTER SELECT (RS0, RS1)
The Register Select inputs allow the microprocessor to select the W65C21 internal registers as presented
Table 2. Full functionality is described under the Functional Description section for Register Access and
Selection.
RESET SIGNAL (RESB)
A low signal (Logic 0) on the Reset line serves to initialize the W65C21, clearing all internal registers (to
Logic 0) and placing all peripheral interface lines (PA and PB) in the input state.
FUNCTIONAL DESCRIPTION
The W65C21 PIA is organized into two independent sections referred to as the A Side and the B Side.
Each section consists of Control Register (CRA, CRB), Data Direction Register (DDRA, DDRB), Output
Register (ORA, ORB), Interrupt Status Control (ISCA, ISCB) and the buffers necessary to drive the
Peripheral Interface buses.
Data Bus Buffers (DBB) interface data from the two sections to the data bus, while the Date Input
Register (DIR) interfaces data from the DBB to the PIA registers. Chip Select and RWB control circuitry
interface to the processor bus control lines. Figure 3 is a block diagram of the W65C21 PIA.
CONTROL REGISTERS (CRA AND CRB)
Table 1 illustrates the bit designation and functions in the two control registers. The individual control
registers allow the microprocessor to control the operation of the Interrupt Control inputs (CA1, CA2, CB1,
CB2), and Peripheral Control outputs (CA2, CB2). Bit 2 in each register controls the addressing of the
Data Direction Registers (DDRA, DDRB) and the Output Registers (ORA, ORB). In addition, two bits (bit
6 and 7) in each control register indicate the status of the Interrupt Status Control input lines (CA1, CA2,
CB1, CB2). These Interrupt Status bits (IRQA1, IRQA2 or IRQB1, IRQB2) are normally interrogated by
the microprocessor during the interrupt service routine to determine the source of an active interrupt.
These two interrupt lines drive the interrupt input (IRQB or NMIB) of the microprocessor.
DATA BUS BUFFERS (DBB)
The Data Bus Buffers are 8-bit bidirectional buffers used for data exchange, on the D0-D7 Data Bus,
between the microprocessor and the PIA. These buffers are tri-state and are capable of driving a two
TTL load when operating in an output mode.
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