CP2400-GQR Silicon Labs, CP2400-GQR Datasheet
CP2400-GQR
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CP2400-GQR Summary of contents
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... GPIO pins may be configured to push-pull or open-drain outputs with two drive levels. GPIO may also be used as digital inputs (CP2400/1/2/3 pullups included) Port Match Capability can wake up host controller using interrupt pin 5 V Tolerant I/O ...
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... CP2400/1/2/3 2 Rev. 1.0 ...
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... LCD Segment Driver ............................................................................. 83 12.2.LCD Configuration ....................................................................................................... 84 12.3.LCD Bias Generation and Contrast Adjustment .......................................................... 85 12.4.LCD Timing Generation ............................................................................................... 87 12.5.Mapping ULP Memory to LCD Pins ............................................................................. 90 12.6.Blinking LCD Segments ............................................................................................... 91 13. Timers ................................................................................................................................. 92 13.1.Timer 0 ....................................................................................................................... 92 13.2.Timer 1 ....................................................................................................................... 96 14. Serial Peripheral Interface (SPI) ..................................................................................... 101 14.1.Signal Descriptions .................................................................................................... 101 14.2.Serial Clock Timing .................................................................................................... 102 CP2400/1/2/3 Rev. 1.0 3 ...
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... CP2400/1/2/3 15. SMBus Interface............................................................................................................... 104 15.1.Supporting Documents .............................................................................................. 104 15.2.SMBus Configuration ................................................................................................. 104 15.3.SMBus Operation....................................................................................................... 105 Document Change List ........................................................................................................ 108 Contact Information .............................................................................................................110 4 Rev. 1.0 ...
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... System Overview CP2400/1/2/3 devices are fixed function LCD drivers that can also be used for expanding GPIO, timekeeping, and increasing available system RAM 256 bytes. The device is controlled using direct and indirect internal registers accessible through the 4-wire SPI or 2-wire SMBus interface. All digital pins on the device are 5 V tolerant ...
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... CP2400/1/2/3 Power On Reset Reset RST Power Net VDD VREG Analog Power GND Power PWR Management SMBA0 SDA SMBus/I2C SCL (2-wire) INT Host Interface Low Power 20 MHz Oscillator External CLK CMOS Clock XTAL1 SmaRTClock Oscillator XTAL2 System Clock Configuration 6 Port I/O Configuration GPIO Expander ...
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... Low Power 20 MHz Oscillator External CLK SYSCLK CMOS Clock XTAL1 SmaRTClock Oscillator XTAL2 System Clock Configuration Figure 1.3. CP2402 Block Diagram Rev. 1.0 CP2400/1/2/3 Port I/O Configuration P0.0/LCD0 P0.1/LCD1 P0.2/LCD2 GPIO Expander Port 0 P0.3/LCD3 Drivers P0.4/LCD4 P0.5/LCD5 P0.6/LCD6 2 x Timer (16-bit) P0.7/LCD7 P1.0/LCD8 P1.1/LCD9 P1 ...
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... CP2400/1/2/3 Power On Reset Reset RST Power Net VDD VREG Analog Power GND Power PWR Management SMBA0 SMBA1 SDA SMBus/I2C SCL (2-wire) INT Host Interface Low Power 20 MHz Oscillator External CLK CMOS Clock XTAL1 SmaRTClock Oscillator XTAL2 System Clock Configuration 8 Port I/O Configuration ...
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... MOSI MOSI NSS NSS GPIO INT GPIO RST GPIO CLK GND GND Figure 1.5. Typical Connection Diagram (SPI Interface) VDD 0 LCD0 LCDn CP240x COM0 COM1 COM2 COM3 Px.x Px.y Rev. 1.0 CP2400/1/2/3 LCD Segment Pin 1 Segment Pin (n+1) COM1 COM2 COM3 COM4 GPIO, Analog, etc. 9 ...
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... CP2400/1/2/3 XTAL1 32.768 kHz XTAL2 VDD MCU SMBA0 SCL SCL SDA SDA GPIO INT GPIO PWR GPIO RST GPIO CLK GND GND Figure 1.6. Typical Connection Diagram (SMBus/I 10 VDD 0 LCD0 LCDn CP240x COM0 COM1 COM2 COM3 Px.x Px Interface) Rev. 1.0 LCD Segment Pin 1 ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. Conditions V > 2 < 2 and GND Rev. 1.0 CP2400/1/2/3 Min Typ Max Units –55 — 125 °C –65 — ...
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... CP2400/1/2/3 3. Electrical Characteristics Table 3.1. Global Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Supply Voltage SYSCLK T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specified Operating Temperature Range Normal Mode Supply Current ( MHz Internal Oscillator divided by 1, SYSCLK = 20 MHz, SPI data rate = 1 Mbps ...
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... V – 0 — — 1.8 V — 3.6 V — DD Rev. 1.0 CP2400/1/2/3 Typ Max Units — — — — See Chart — V — — — — See Chart — — 0.6 — 0.1 See Chart — ...
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... CP2400/1/2/3 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Typical VOH (High Drive Mode Load Current (mA) Typ rive urre Figure 3 ...
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... Typical VOL (High Drive Mode) 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 1.5 1.2 0.9 0.6 0 Load Current (mA) Figure 3.2. Typical VOL Rev. 1.0 CP2400/1/2/3 VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V -30 -20 - VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1. ...
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... CP2400/1/2/3 Table 3.3. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters RST Input High Voltage RST Input Low Voltage RST Input Pullup Current 1 V Ramp Time for Power On DD Power on Reset Delay (T ) PORDelay from Start of Ramp until the Reset ...
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... Pinout and Package Definitions Table 1. CP2400/1/2/3 Pin Definitions Name Pin Numbers 48-pin 32-pin SPI 2 SPI XTAL1 XTAL2 GND CAP CLK RST INT ...
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... CP2400/1/2/3 Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P0 LCD2 P0 LCD3 P0 LCD4 P0 LCD5 P0 LCD6 P0 LCD7 P1 LCD8 P1 LCD9 P1 LCD10 P1 ...
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... Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P2 — — LCD18 P2 — — LCD19 P2.0 — — COM0 P2.1 — — COM1 P2.2 — — COM2 P2.3 — — COM3 P2 — — ...
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... CP2400/1/2/3 Table 1. CP2400/1/2/3 Pin Definitions (Continued) Name Pin Numbers 48-pin 32-pin SPI 2 SPI P3 — — LCD30 P3 — — LCD31 P4 — — COM0 P4 — — COM1 P4 — — COM2 P4 — — COM3 20 Type Description ...
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... XTAL1 1 XTAL2 2 VDD 3 GND 4 P4.3/COM3 5 CP2400 - GQ P4.2/COM2 6 Top View P4.1/COM1 7 P4.0/COM0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.1. CP2400-GQ Pinout (SPI Interface) XTAL1 1 XTAL2 2 VDD 3 GND 4 P4.3/COM3 5 CP2401 - GQ P4.2/COM2 6 Top View P4.1/COM1 7 P4.0/COM0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.2. CP2401-GQ Pinout (SMBus/I Rev. 1.0 CP2400/1/2/3 P0 ...
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... CP2400/1/2/3 XTAL1 1 2 XTAL2 3 VDD GND 4 P4.3/COM 3 5 P4.2/COM 2 6 P4.1/COM 1 7 P4.0/COM 0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.3. CP2400-GM Pinout (SPI Interface) XTAL1 1 2 XTAL2 3 VDD GND 4 P4.3/COM3 5 P4.2/COM2 6 P4.1/COM1 7 P4.0/COM0 8 P3.7/LCD31 9 P3.6/LCD30 10 P3.5/LCD29 11 P3.4/LCD28 12 Figure 4.4. CP2401-GM Pinout (SMBus ...
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... GND P2.0/COM0 8 Figure 4.5. CP2402-GM Pinout (SPI Interface) 1 XTAL1 2 XTAL2 3 VDD CP2403 - GM 4 GND Top View 5 P2.3/COM3 6 P2.2/COM2 7 P2.1/COM1 GND 8 P2.0/COM0 Figure 4.6. CP2403-GM Pinout (SMBus Interface) Rev. 1.0 CP2400/1/2/3 24 P0.0/LCD0 P0.1/LCD1 23 P0.2/LCD2 22 P0.3/LCD3 21 20 P0.4/LCD4 19 P0.5/LCD5 P0.6/LCD6 18 P0.7/LCD7 17 P0.0/LCD0 24 23 P0.1/LCD1 22 P0.2/LCD2 P0.3/LCD3 21 P0 ...
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... CP2400/1/2/3 Figure 4.7. QFN-48 Package Drawing 24 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VKKD-4 except for features D2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components ...
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... Figure 4.8. QFN-48 Landing Diagram CP2400/1/2/3 Rev. 1.0 25 ...
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... CP2400/1/2/3 Dimension Notes: General 3. All dimensions shown are in millimeters (mm) unless otherwise noted. 4. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 5. This Land Pattern Design is based on IPC-SM-782 guidelines. 6. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. CP2400/1/2/3 Min Nom Max — ...
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... CP2400/1/2/3 Figure 4.10. TQFP-48 Recommended PCB Land Pattern Table 4.3. TQFP-48 PCB Land Pattern Dimensions Dimension Notes: General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design: 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µ ...
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... Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. CP2400/1/2/3 Dimension Min E2 3. ...
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... CP2400/1/2/3 Figure 4.12. Typical QFN-32 Landing Diagram 30 Rev. 1.0 ...
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... array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 CP2400/1/2/3 MIN MAX 4.80 4.90 4.80 4.90 ...
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... Clocking Options CP2400/1/2/3 devices include a 20 MHz internal oscillator that is selected as the system clock source upon reset. Additional clocking options include an external CMOS clock input, the internal oscillator divided and the SmaRTClock real time clock oscillator. The system clock source is selected using the CLKSEL register. The system clock selection may always be overridden by an external CMOS clock if the CLKOVR bit (MSCN ...
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... Indicates the device revision. For example 0x01 indicates Revision Reserved R/W R/W R Function Section “9.2. RAM Preservation Mode” on page REVID[7:0] R/W Varies Varies Varies Function Rev. 1.0 CP2400/1/2 INTCTL OSCEN EXTCTL R for information on how Varies Varies Varies 33 ...
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... CP2400/1/2/3 6. Internal Registers and Memory The CP2400/1/2/3 is controlled by internal registers and provides the system with up to 256 bytes of additional RAM. The internal registers and memory are controlled through an indirect interface accessible through a 4-wire SPI interface (CP2400/2) or 2-wire SMBus/I RAM is shown in Figure 6.1. The internal registers are listed in “6.3. Internal Registers” on page 37. ...
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... GPIO pin or updating the SmaRTClock registers. Writes one or more bytes to registers with sequential addresses. Reads one or more bytes from sequential RAM locations. Writes one or more bytes to sequential RAM locations. ADDRL DATA 0 DATA 1 ADDRL WAIT DATA 0 Figure 6.2. SPI Transfer Rev. 1.0 CP2400/1/2/3 DATA N DATA N 35 ...
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... CP2400/1/2/3 6.2. Accessing Internal Registers and RAM over the SMBus Interface The SMBus interface supports 6 commands which provide access to all internal registers and RAM. The six commands are listed in Table 6.2. Detailed information on the SMBus interface including bus timing can be found in Section “15. SMBus Interface” on page 104. ...
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... Internal Registers The CP2400/1/2/3 internal registers are grouped into categories based on function. The memory map is organized to minimize register access time, by sequentially locating registers that can be read or written with a single block read or write. Table 6.3 shows the register memory map for all registers available on the device. ...
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... CP2400/1/2/3 Table 6.3. Internal Register Memory Map (Continued) Register Address ULPMEM03 0x84 ULP Memory Byte 3 ULPMEM04 0x85 ULP Memory Byte 4 ULPMEM05 0x86 ULP Memory Byte 5 ULPMEM06 0x87 ULP Memory Byte 6 ULPMEM07 0x88 ULP Memory Byte 7 ULPMEM08 0x89 ULP Memory Byte 8 ULPMEM09 0x8A ...
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... Port I/O Input and Status Registers PMATCHST 0xD0 Port Match Status P0IN 0xD1 Port 0 Input P1IN 0xD2 Port 1 Input P2IN 0xD3 Port 2 Input P3IN 0xD4 Port 3 Input P4IN 0xD5 Port 4 Input CP2400/1/2/3 Description Rev. 1.0 Preserved Page No ...
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... Interrupt Sources The CP2400/1/2/3 can alert the host processor when any of the interrupt source events listed in Table 7.1 triggers an interrupt. The CP2400/1/2/3 alerts the host of pending interrupt events by setting the appropriate flags in the interrupt status registers and driving the INT pin low. The INT pin will remain asserted until all interrupt flags for enabled interrupts have been cleared by the host ...
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... SmaRTClock oscillator failure detected. 2:1 Unused Read = 00b. 0 PMINT Port Match Interrupt Flag Port Match events detected since PMINT was last cleared. 1: Port Match event pending Reserved ALRM RTCFAIL Function Rev. 1.0 CP2400/1/2 PMINT ...
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... CP2400/1/2/3 SFR Definition 7.2. INT0RD: Interrupt Status Register 0 (Read-Only) Bit 7 6 Name Type R R Reset 0 0 Address = 0x40 Bit Name 7:6 Unused Read = 00b. 5 Reserved Read = 0. 4 ALRMR SmaRTClock Alarm Interrupt Flag SmaRTClock Alarm pending since ALRM was last cleared. 1: SmaRTClock Alarm pending. ...
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... Read = 11b. Write = don’t care. 0 EPMINT Enable Port Match Interrupt. This bit sets the masking of Port Match Interrupt. 0: Disable Port Match Interrupt. 1: Enable interrupt requests generated by Port Match events Reserved EALRM ERTCFAIL R/W R/W R Function Rev. 1.0 CP2400/1/2 EPMINT R/W R/W R ...
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... CP2400/1/2/3 SFR Definition 7.4. INT1: Interrupt Status Register 1 (Self-Clearing) Bit 7 6 Name Type R R Reset 0 0 Address = 0x44 Bit Name 7:5 Unused Read = 000b. 4 RSTC Reset Complete Interrupt Flag. 0: Device has not yet finished initialization. 1: Device is ready for communication over the host interface. ...
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... Timer 1 has overflowed or a capture event has occurred since T1F was last cleared. 2 T0FR Timer 0 Overflow Interrupt Flag. 0: Timer 0has not overflowed since T0F was last cleared. 1: Timer 0 has overflowed since T0F was last cleared. 1:0 Unused Read = 00b RSTCR T1FR Function Rev. 1.0 CP2400/1/2 T0FR ...
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... CP2400/1/2/3 SFR Definition 7.6. INT1EN: Interrupt Enable Register 1 Bit 7 6 Name Type R/W R/W Reset 1 1 Address = 0x31 Bit Name 7:5 Unused Read = 111. Write = don’t care. 4 ERSTC Enable Reset Complete Interrupt. 0: Disable Reset Complete interrupt. 1: Enable interrupt requests generated when device is ready for communication over the host interface ...
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... All interrupts (except SmaRTClock Oscillator Fail) are enabled. The CP2400/1/2/3 has two reset sources that place the device in the reset state. The method of entry to the reset state determines the amount of time spent in reset. Each of the following reset sources is described in the following sections: ...
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... Logic HIGH Logic LOW 8.3. External Pin Reset The RST pin provides a means for external circuitry to force the CP2400/1/2/3 into a reset state. Asserting RST for at least T will cause the CP2400/1/2/3 to enter the reset state recommended to drive RST with a push-pull RST driver or add an external pull-up resistor to avoid erroneous noise-induced resets. The CP2400/1/2/3 will exit the reset state and generate a Reset Complete Interrupt approximately one T detected on RST ...
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... Power Modes The CP2400/1/2/3 has four power modes that can be used to minimize overall system power consumption. The power modes vary in device functionality and wake-up methods. Each of the following power modes is explained in the following sections: Normal Mode (Device Fully Functional) ...
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... In RAM Preservation Mode, the internal oscillator is disabled and the SmaRTClock oscillator provides the system clock. RAM Preservation Mode should be used when the CP2400/1/2/3 needs to be active for a prolonged period of time in which communication with the host microcontroller is not required. Examples of this include preserving the contents of RAM or using the fully featured Active port match capabilities ...
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... CLK pin. The SmaRTClock should be disabled by writing 0x00 to the indirect RTC0CN register instead of setting the RTCDIS bit (ULPCN.4) while entering ULP LCD Mode. When the SmaRTClock is disabled, SmaRTClock alarm and SmaRTClock oscillator fail detection functionality is no longer available. CP2400/1/2/3 Rev. 1.0 51 ...
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... CP2400/1/2/3 9.4. Ultra Low Power SmaRTClock Mode In Ultra Low Power SmaRTClock Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block. LCD functionality is disabled. The ULP block allows the device to maintain a real time clock and detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events ...
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... Shutdown Mode Shutdown mode is the lowest power mode for the CP2400/1/2/3. All device functionality is disabled in this mode and a reset is required to wake up the device. This mode is typically used when the device is not needed for prolonged periods of time. From Normal Mode, the device can be placed in shutdown mode using the following procedure: 1 ...
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... CP2400/1/2/3 SFR Definition 9.1. ULPCN: Ultra Low Power Control Register Bit 7 6 Name Type R/W R/W Reset 0 0 Address = 0xA2 Bit Name 7:5 Unused Read = 000b. Write = Don’t Care. 4 RTCDIS Ultra Low Power Mode SmaRTClock Disable. When set to 1, the SmaRTClock oscillator will be disabled two SmaRTClock cycles after entry into ULP Mode ...
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... Source of last wake up was a SmaRTClock Alarm. 0 ULPPM Ultra Low Power Port Match Wake Up Indicator. 0: Source of last wake up was not a ULP Port Match. 1: Source of last wake up was a ULP Port Match RTCFAIL Function Rev. 1.0 CP2400/1/2 RTCALRM ULPPM varies 55 ...
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... CP2400/1/2/3 9.7. Port Match Functionality in the Ultra Low Power Modes The ultra low power LCD and SmaRTClock modes support port match wake-up. ULP SmaRTClock mode supports port match on all P0, P1, P2, and P3 pins. ULP LCD mode supports port match on P3.3, P3.4, P3.5, P3.6, and P3.7. ULP Port Match events can be generated on rising or falling edges; however, all events are configured to the same polarity using the ULPPMPOL bit (ULPCN ...
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... See “12.5. Mapping ULP Memory to LCD Pins” on page 90 for information on how ULP Memory is used with the LCD function. See Section “9.7. Port Match Functionality in the Ultra Low Power Modes” on page 56 for information on how ULP Memory is used with the ULP Port Match function ULPMEMn R/W R/W R Function Rev. 1.0 CP2400/1/2 R/W R/W R ...
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... CP2400/1/2/3 9.8. Disabling Secondary Device Functions The MSCN and MSCF registers provide additional ways of saving power by disabling unnecessary functionality. SFR Definition 9.4. MSCN: Master Control Register Bit 7 6 Name RTCBYP CLEAR ADRINV Type R/W R/W Reset 0 0 Address = 0xA0 Bit Name 7 RTCBYP SmaRTClock Oscillator Bypass. ...
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... Note: When the band gap is configured for low power mode with loose voltage regulation, the LCD0CF register should be adjusted so that charge pump cycles occur at least once every 2 ms Reserved Reserved R/W R/W R Function Rev. 1.0 CP2400/1/2 Reserved Reserved CPBYP R/W R/W R ...
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... CP2400/1/2/3 10. Port Input/Output CP2400/1/2/3 devices have 36 (48-pin packages (32-pin packages) multi-function I/O pins. Port pins are organized as byte-wide ports and may be used for general purpose I/O, generating a Port Match interrupt, or for an analog function (e.g., LCD). Note: The port match functionality described in this chapter only applies when the device is awake (Normal and Idle Power Modes) ...
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... Logic Value (Port Latch) PxMDI.x (1 for digital) (0 for analog) To/From Analog Peripheral PxIN.x – Input Logic Value (Reads 0 when pin is configured as an analog I/O) Figure 10.2. Port I/O Cell Block Diagram CP2400/1/2/3 or GND supply rails based on the output DD VDD VDD GND Rev. 1.0 (WEAK) PORT PAD ...
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... CP2400/1/2/3 10.1.3. Interfacing Port I and 3.3 V Logic All Port I/Os configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8 to 2.2 V, the I/O may also interface to digital logic operating between 3 external pull-up resistor to the higher supply voltage is typically required for most systems ...
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... No port mismatch events have been detected on P1 port mismatch event is present on P1. 0 P0M Port 0 Match port mismatch events have been detected on P0 port mismatch event is present on P0 P4M P3M R/W R/W R Function Rev. 1.0 CP2400/1/2 P2M P1M P0M R/W R/W R ...
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... CP2400/1/2/3 SFR Definition 10.2. PnMSK: Port n Mask Register Bit 7 6 Name Type 0 0 Reset Address: P0MSK = 0xC9; P1MSK = 0xCA; P2MSK = 0xCB; P3MSK = 0xCC; P4MSK = 0xCD Bit Name 7:0 PnMSK[7:0] Port n Mask Value. Selects the Pn pins to be compared with the corresponding bits in PnMATCH. 0: Pn.x pin pad logic value is ignored and cannot cause a Port Mismatch event. ...
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... The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRIVE) registers. The default is low drive strength. See Table 3.2 on page 13 for the difference in output drive strength between the two modes. CP2400/1/2/3 Rev. 1.0 65 ...
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... CP2400/1/2/3 SFR Definition 10.4. PnOUT: Port n Output Latch Bit 7 6 Name Type 1 1 Reset Address: P0OUT = 0xB0; P1OUT = 0xB1; P2OUT = 0xB2; P3OUT = 0xB3; P4OUT = 0xB4 Bit Name 7:0 PnOUT[7:0] Port n Output Latch. Sets or reads the Port latch logic value. 0: Pn.x output latch is logic LOW. ...
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... Reset Address: P0MDO = 0xBA; P1MDO = 0xBB; P2MDO = 0xBC; P3MDO = 0xBD; P4MDO = 0xBE Bit Name 7:0 PnMDO[7:0] Pn Output Configuration Bits. 0: Corresponding Pn.x Output is open-drain. 1: Corresponding Pn.x Output is push-pull P0MDI[7:0] R Function PnMDO[7:0] R Function Rev. 1.0 CP2400/1/2 ...
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... CP2400/1/2/3 SFR Definition 10.8. PnDRIVE: Port n Drive Strength Bit 7 6 Name Type 0 0 Reset Address: P0DRIVE = 0xBF; P1DRIVE = 0xC0; P2DRIVE = 0xC1; P3DRIVE = 0xC2; P4DRIVE = 0xC3 Bit Name 7:0 PnDRIVE[7:0] Pn Drive Strength Configuration Bits. Configures digital I/O Port cells to high or low output drive strength. 0: Corresponding Pn.x has low output drive strength. ...
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... SmaRTClock (Real Time Clock) CP2400/1/2/3 devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals ...
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... SmaRTClock Interface The SmaRTClock Interface consists of three registers: RTCKEY, RTCADR, and RTCDAT. These interface registers are located on the CP2400/1/2/3 register map and provide access to the SmaRTClock internal registers listed in Table 11.1. The SmaRTClock internal registers can only be accessed indirectly through the SmaRTClock Interface. ...
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... Autoincrement is always enabled. Notes: Autoincrement should only be used with block reads/writes. When using single-byte reads/writes, RTCADR must be written before each data read or write. When using SMBus to perform a block read/write, the RTCADR register must be written using the REGSET command. CP2400/1/2/3 Rev. 1.0 71 ...
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... CP2400/1/2/3 SFR Definition 11.1. RTCKEY: SmaRTClock Lock and Key Bit 7 6 Name Type Reset 0 0 Address = 0x0A Bit Name 7:0 RTC0ST SmaRTClock Interface Lock/Key and Status. Locks/unlocks the SmaRTClock interface when written. Provides lock status when read. Read: 0x00: SmaRTClock Interface is locked. 0x01: SmaRTClock Interface is locked. ...
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... Name Type Reset 0 0 Address = 0x0C Bit Name 7:0 RTCDAT SmaRTClock Data Bits. Holds data transferred to/from the internal SmaRTClock register selected by RTCADR SHORT R R varies Function RTCDAT[7:0] R Function Rev. 1.0 CP2400/1/2 ADDR[3:0] R/W varies varies varies ...
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... CP2400/1/2/3 11.2. SmaRTClock Clocking Sources The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of operation: crystal mode, and self-oscillate mode. The oscillation frequency is 32.768 kHz in crystal mode and can be programmed in the range of sub 20 kHz to above 40 kHz in self-oscillate mode ...
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... Crystal Load Capacitance 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Equivalent Capacitance seen on XTAL1 and XTAL2 4.0 pF 8.0 pF 4.5 pF 9.0 pF 5.0 pF 10.0 pF 5.5 pF 11.0 pF 6.0 pF 12.0 pF 6.5 pF 13.0 pF 7.0 pF 14.0 pF 7.5 pF 15.0 pF 8.0 pF 16.0 pF 8.5 pF 17.0 pF 9.0 pF 18.0 pF 9.5 pF 19.0 pF 10.5 pF 21.0 pF 11.5 pF 23.0 pF 12.5 pF 25.0 pF 13.5 pF 27.0 pF Rev. 1.0 CP2400/1/2/3 75 ...
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... CP2400/1/2/3 11.2.4. Automatic Gain Control and SmaRTClock Bias Doubling Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it may be enabled during crystal startup ...
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... The SmaRTClock alarm event can be configured to generate a wake-up from a low power mode, or generate an interrupt. See Section “7. Interrupt Sources” on page 40, Section “9. Power Modes” on page 49, and for more information. The following steps can be used to set up a SmaRTClock Alarm: CP2400/1/2/3 Rev. 1.0 77 ...
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... CP2400/1/2/3 1. Disable SmaRTClock Alarm Events (RTC0AEN = 0). 2. Set the ALARMn registers to the desired value. 3. Enable SmaRTClock Alarm Events (RTC0AEN = 1). Notes: The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm Events (RTC0AEN = 0). Disabling (RTC0AEN = 0) then re-enabling Alarm Events (RTC0AEN = 1) after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32 ...
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... Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle OSCFAIL RTC0TR RTC0AEN R/W R/W R/W Varies 0 0 Function Read: 0: SmaRTClock alarm event flag is de-asserted. 1: SmaRTClock alarm event flag is asserted. Rev. 1.0 CP2400/1/2 ALRM RTC0SET RTC0CAP R/W R/W R Write: 0: Disable Auto Reset. 1: Enable Auto Reset. 79 ...
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... CP2400/1/2/3 Internal Register Definition 11.5. RTC0XCN: SmaRTClock Oscillator Control Bit 7 6 Name AGCEN XMODE Type R/W R/W Reset 0 0 SmaRTClock Address = 0x05 Bit Name 7 AGCEN SmaRTClock Oscillator Automatic Gain Control (AGC) Enable. 0: AGC disabled. 1: AGC enabled. 6 XMODE SmaRTClock Oscillator Mode. Selects Crystal or Self Oscillate Mode. ...
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... Load capacitance has reached it programmed value. 5:4 Unused Read = 00b; Write = Don’t Care. 3:0 LOADCAP Load Capacitance Programmed Value. Holds the user’s desired value of the load capacitance. See Table 11.2 on page 75 Function Rev. 1.0 CP2400/1/2 LOADCAP R ...
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... CP2400/1/2/3 Internal Register Definition 11.7. CAPTUREn: SmaRTClock Timer Capture Bit 7 6 Name Type R/W R/W Reset 0 0 SmaRTClock AddressCAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03. Bit Name 7:0 CAPTURE[31:0] SmaRTClock Timer Capture. These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit SmaRT- Clock timer. Data is transferred to or from the SmaRTClock timer when the RTC0SET or RTC0CAP bits are set ...
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... LCD Segment Driver CP2400/1/2/3 devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3- mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast control which is independent of the VDD supply voltage. LCD timing is derived from the SmaRTClock oscillator to allow precise control over the refresh rate ...
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... CP2400/1/2/3 12.2. LCD Configuration The LCD segment driver supports multiple mux options: static, 2-mux, 3-mux, and 4-mux mode. It also supports 1/2 and 1/3 bias options. The desired mux mode and bias is configured through the LCD0CN register. SFR Definition 12.1. LCD0CN: LCD0 Control Register Bit 7 6 Name ...
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... Read = 0000. Write = Don’t Care. 3:0 CNTRST Contrast Adjustment. Selects the on-chip charge pump output voltage. 0000: 2.60 V 0001: 2.60 V 0010: 2.66 V 0011: 2.72 V 0100: 2.78 V 0101: 2.84 V 0110: 2.90 V 0111: 2.96 V 1000: 3.02 V 1001: 3.08 V 1010: 3.14 V 1011: 3.20 V 1100: 3.26 V 1101: 3.32 V 1110: 3.38 V 1111: 3. R/W R Function Rev. 1.0 CP2400/1/2 CNTRST R ...
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... CP2400/1/2/3 SFR Definition 12.3. LCD0CF: LCD Configuration Bit 7 6 Name Reserved Type R/W Reset 1 0 Address = 0x97 Bit Name 7:4 Reserved Read = 10b. Must Write 10b. 5:0 CPCYC[5:0] Charge Pump Cycle Period. The number of SmaRTClock oscillator periods between charge pump cycles is CPCYC[5:0]+1. The time between charge pump cycles should not exceed 2 ms. ...
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... Sets the LCD refresh rate according to the following equation: LCD Refresh Rate R/W R/W R Function SmaRTClock Oscillator Frequency = ------------------------------------------------------------------------------------------- - 4 mux_mode LCD0DIV LCD0DIV[7:0] R Function SmaRTClock Oscillator Frequency = ------------------------------------------------------------------------------------------- - 4 mux_mode LCD0DIV 1 + Rev. 1.0 CP2400/1/2 LCD0DIV[9:8] R/W R 87 ...
Page 88
... CP2400/1/2/3 SFR Definition 12.6. LCD0TOGR: LCD Toggle Rate Bit 7 6 Name Type R/W R/W Reset 0 0 Address = 0x9A Bit Name 7:4 Unused Read = 0000. Write = Don’t Care. 3:0 TOGR[3:0] LCD Toggle Rate Divider . Sets the LCD Toggle Rate according to the following equation: LCD Toggle Rate 0000: Reserved ...
Page 89
... Read = 000b. Must Write 000b. 4:3 CPCLK[1:0] Charge Pump Clock Select. 00: 1 MHz charge pump clock (normal operation). 01: 2 MHz charge pump clock. 10: 0.5 MHz charge pump clock. 11: 0.67 MHz charge pump clock. 2:0 Reserved Read = 000b. Must Write 000b CPCLK[1:0] R/W R/W R Function Rev. 1.0 CP2400/1/2 R/W R/W R ...
Page 90
... CP2400/1/2/3 12.5. Mapping ULP Memory to LCD Pins The ULP memory is organized in 16 bytes (32 half-bytes or nibbles), each nibble controlling 1 LCD output pin. Each LCD output pin can control LCD segments depending on the selected mux mode. The least significant bit of each nibble controls the segment connected to the backplane signal COM0 and the most significant bit of each nibble controls the segment connected to the backplane signal COM3 ...
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... Each bit maps to a specific LCD segment connected to the LCD0 and LCD1 segment pins. A value of 1 indicates that the segment is blinking. A value of 0 indicates that the segment is not blinking. This bit to segment mapping is the same as the ULPMEM00 register LCD0BLINK[7:0] R/W R/W R Function Rev. 1.0 CP2400/1/2 R/W R/W R ...
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... CP2400/1/2/3 13. Timers CP2400/1/2/3 devices include two 16-bit auto-reload timers. These timers can be used to measure time intervals and generate periodic interrupt requests. Both timers can be clocked from the system clock source divided by 12. Timer 1 has an additional SmaRTClock divided by 8 input and capture mode that can be used to measure the SmaRTClock oscillation frequency with respect to the system clock ...
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... Timer 0 overflows. 4:3 Unused Read = 00b. Write = Don’t Care. 2 TR0 Timer 0 Run Control. Timer 0 is enabled by setting this bit to 1. 1:0 Unused Read = 00b. Write = Don’t Care TF0LEN R/W R/W R Function Rev. 1.0 CP2400/1/2 TR0 R/W R/W R ...
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... CP2400/1/2/3 SFR Definition 13.2. TMR0RLL: Timer 0 Reload Register Low Byte Bit 7 6 Name Type Reset 1 0 SFR Address = 0x50 Bit Name 7:0 TMR0RLL[7:0] Timer 0 Reload Register Low Byte. TMR0RLL holds the low byte of the reload value for Timer 0. SFR Definition 13.3. TMR0RLH: Timer 0 Reload Register High Byte ...
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... SFR Definition 13.5. TMR0H Timer 0 High Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x53 Bit Name 7:0 TMR0H[7:0] Timer 0 High Byte. Contains the high byte of the 16-bit Timer TMR0L[7:0] R Function TMR0H[7:0] R Function Rev. 1.0 CP2400/1/2 ...
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... CP2400/1/2/3 13.2. Timer 1 Timer 16-bit timer formed by two 8-bit SFRs: TMR1L (low byte) and TMR1H (high byte). Timer 1 operates in 16-bit auto-reload mode and is clocked by the system clock divided SmaRTClock divided the 16- bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 1 reload registers (TMR1RLH and TMR1RLL) is loaded into the Timer 1 register as shown in Figure 13 ...
Page 97
... Counts = (24500000 12) / 498 = 16333333 / 498 = 32797 Hz. This mode allows software to determine the SmaRTClock oscillator frequency when the SmaRTClock oscillator is being used in self-oscillate mode without a crystal. SYSCLK / 12 SmaRTClock / 8 Figure 13.3. Timer 1 Capture Mode Block Diagram TCLK TR1 TMR1L TMR1H Capture TF1CEN TMR1RLL TMR1RLH Rev. 1.0 CP2400/1/2/3 Interrupt 97 ...
Page 98
... CP2400/1/2/3 SFR Definition 13.6. TMR1CN: Timer 1 Control Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Address = 0x59 Bit Name 7:6 Unused Read = 00b. Write = Don’t Care. 5 TF1LEN Timer 1 Low Byte Interrupt Enable. When set to 1, this bit enables Timer 1 Low Byte interrupts. If Timer 1 interrupts are enabled, an interrupt will be generated when the low byte of Timer 1 overflows ...
Page 99
... Type Reset 0 0 SFR Address = 0x56 Bit Name 7:0 TMR1RLH[7:0] Timer 1 Reload Register High Byte. TMR1RLH holds the high byte of the reload value for Timer TMR1RLL[7:0] R Function TMR1RLH[7:0] R Function Rev. 1.0 CP2400/1/2 ...
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... CP2400/1/2/3 SFR Definition 13.9. TMR1L: Timer 1 Low Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x57 Bit Name 7:0 TMR1L[7:0] Timer 1 Low Byte. Contains the low byte of the 16-bit Timer 1. SFR Definition 13.10. TMR1H Timer 1 High Byte Bit 7 6 Name Type Reset 0 0 SFR Address = 0x58 ...
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... Serial Peripheral Interface (SPI) CP2400/2 devices have a 4-wire Serial Peripheral Interface which provides access to the internal registers and memory. A typical connection to a SPI master is shown in Figure 14.1. Master Device GPIO Figure 14.1. SPI Connection Diagram 14.1. Signal Descriptions The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below. ...
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... CP2400/1/2/3 14.2. Serial Clock Timing The clock to data relationship is shown in Figure 14.2. If the SPI master is a C8051 microcontroller, its SPI peripheral must be configured for Mode 0 communication (CKPOL = 0, CKPHA = 0). The maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency ...
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... T SYSCLK SYSCLK SYSCLK SYSCLK — SYSCLK T CKL T T SIS SIH T SOH Figure 14.3. SPI Slave Timing Rev. 1.0 CP2400/1/2/3 Max Units — ns — SYSCLK SYSCLK — ns — ns — ns — SYSCLK ...
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... CP2400/1/2/3 15. SMBus Interface The SMBus I/O interface is a two-wire, bi-directional serial bus that can be used to access the internal registers and memory on CP2401/3 devices. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data ...
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... The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. SLA5-0 R/W D7 ACK Figure 15.2. SMBus Transaction 2 C, which allows devices with different speed Rev. 1.0 CP2400/1/2/3 The master D6-0 Data Byte NACK STOP 105 ...
Page 106
... Slave Address Selection CP2400/1/2/3 devices can have one of 2 possible 7-bit, left-justified slave addresses: 0x74 and 0x76. The least significant bit of the slave address is set by the SMBA0 pin. The remaining bits in the slave address are fixed. The bit following the least significant address bit is used to indicate whether the current transfer is a read or a write ...
Page 107
... When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 50 µs. 1 Reserved Read = 00b. Must write 00b. :0 Note: This register has a reset value of 0x00 in devices that do not support SMBus BUSY EXTHOLD SMBTOE SMBFTE R R/W R Function Rev. 1.0 CP2400/1/2 Reserved R/W R 107 ...
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... CP2400/1/2 OCUMENT HANGE IST Revision 0.2 to Revision 1.0 Updated Electrical Specifications to remove TBDs and specify min/max parameters. Updated Reset Values for various registers. Updated Register Description for LCD0PWR register. 108 Rev. 1.0 ...
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... N : OTES CP2400/1/2/3 Rev. 1.0 109 ...
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... CP2400/1/2 ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...