DEV KIT FOR F005/006/007

C8051F005DK

Manufacturer Part NumberC8051F005DK
DescriptionDEV KIT FOR F005/006/007
ManufacturerSilicon Laboratories Inc
TypeMCU
C8051F005DK datasheet
 

Specifications of C8051F005DK

ContentsEvaluation Board, Power Supply, USB Cables, Adapter and DocumentationProcessor To Be EvaluatedC8051F01x
Interface TypeUSBSilicon ManufacturerSilicon Labs
Core Architecture8051Silicon Core NumberC8051F005
Silicon Family NameC8051F00xLead Free Status / RoHS StatusContains lead / RoHS non-compliant
For Use With/related ProductsSilicon Laboratories C8051 F005/006/007Other names336-1188
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
Page 1/171

Download datasheet (2Mb)Embed
Next
Mixed-Signal 32KB ISP FLASH MCU Family
ANALOG PERIPHERALS
-
SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor ( 3C)
-
Two 12-bit DACs
-
Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
-
Voltage Reference
2.4V; 15 ppm/C
Available on External Pin
-
Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
-
On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
-
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
-
Inspect/Modify Memory and Registers
-
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
-
IEEE1149.1 Compliant Boundary Scan
-
Low Cost Development Kit
ANALOG PERIPHERALS
12-Bit
DAC
12-Bit
DAC
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
Copyright © 2003 by Silicon Laboratories
Rev. 1.7 11/03
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
HIGH SPEED 8051 C CORE
-
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
-
Up to 25MIPS Throughput with 25MHz Clock
-
21 Vectored Interrupt Sources
MEMORY
-
256 Bytes Internal Data RAM (F000/01/02/10/11/12)
-
2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
-
32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
-
4 Byte-Wide Port I/O; All are 5V tolerant
-
Hardware SMBus
Serial Ports Available Concurrently
-
Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
-
Four General Purpose 16-bit Counter/Timers
-
Dedicated Watch-Dog Timer
-
Bi-directional Reset
CLOCK SOURCES
-
Internal Programmable Oscillator: 2-to-16MHz
-
External Oscillator: Crystal, RC,C, or Clock
-
Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................ 2.7V to 3.6V
-
Typical Operating Current: 12.5mA @ 25MHz
-
Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40C to +85C
DIGITAL I/O
TEMP
PCA
SENSOR
SAR
SMBus
PGA
ADC
SPI Bus
UART
VREF
Timer 0
Timer 1
+
+
-
Timer 2
-
VOLTAGE
Timer 3
COMPARATORS
CLOCK
DEBUG
JTAG
CIRCUIT
CIRCUITRY
256/2304 B
21
SRAM
INTERRUPTS
CONTROL
TM
TM
TM
(I2C
Compatible), SPI
, and UART
SANITY

C8051F005DK Summary of contents

  • Page 1

    Mixed-Signal 32KB ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC  12-Bit (C8051F000/1/2, C8051F005/6/7)  10-bit (C8051F010/1/2, C8051F015/6/7) 1LSB INL; No Missing Codes   Programmable Throughput up to 100ksps  External Inputs; Programmable as Single- ...

  • Page 2

    TABLE OF CONTENTS 1. SYSTEM OVERVIEW ......................................................................................................... 8 Table 1.1. Product Selection Guide .....................................................................................................................8 Figure 1.1. C8051F000/05/10/15 Block Diagram ...............................................................................................9 Figure 1.2. C8051F001/06/11/16 Block Diagram .............................................................................................10 Figure 1.3. C8051F002/07/12/17 Block Diagram .............................................................................................11 TM 1.1. CIP-51 CPU .........................................................................................................................................12 Figure 1.4. Comparison ...

  • Page 3

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................38 Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................39 6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only).......................................................................... 40 Figure 6.1. 10-Bit ADC Functional Block Diagram..........................................................................................40 6.1. Analog Multiplexer and PGA..................................................................................................................40 6.2. ADC Modes of Operation........................................................................................................................41 Figure 6.2. 10-Bit ...

  • Page 4

    Figure 10.5. DPH: Data Pointer High Byte .......................................................................................................74 Figure 10.6. PSW: Program Status Word..........................................................................................................75 Figure 10.7. ACC: Accumulator........................................................................................................................76 Figure 10. Register .................................................................................................................................76 10.4. INTERRUPT HANDLER ...................................................................................................................77 Table 10.4. Interrupt Summary..........................................................................................................................78 Figure 10.9. IE: Interrupt Enable.......................................................................................................................79 Figure 10.10. IP: ...

  • Page 5

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.4. XBR1: Port I/O CrossBar Register 1 ..........................................................................................107 Figure 15.5. XBR2: Port I/O CrossBar Register 2 ..........................................................................................108 15.3. General Purpose Port I/O...................................................................................................................109 15.4. Configuring Ports Which are not Pinned Out....................................................................................109 Figure 15.6. P0: Port0 Register .......................................................................................................................109 Figure ...

  • Page 6

    Table 18.2. Oscillator Frequencies for Standard Baud Rates ..........................................................................136 Figure 18.8. SBUF: Serial (UART) Data Buffer Register...............................................................................136 Figure 18.9. SCON: Serial Port Control Register............................................................................................137 19. TIMERS ............................................................................................................................. 138 19.1. Timer 0 and Timer 1 ..........................................................................................................................138 Figure 19.1. T0 Mode 0 ...

  • Page 7

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 21.1. Boundary Data Register Bit Definitions.......................................................................................165 Figure 21.2. DEVICEID: JTAG Device ID Register ......................................................................................166 21.2. Flash Programming Commands.........................................................................................................167 Figure 21.3. FLASHCON: JTAG Flash Control Register...............................................................................168 Figure 21.4. FLASHADR: JTAG Flash Address Register..............................................................................168 Figure 21.5. FLASHDAT: JTAG Flash ...

  • Page 8

    SYSTEM OVERVIEW The C8051F000 family are fully integrated mixed-signal System on a Chip MCUs with a true 12-bit multi-channel ADC (F000/01/02/05/06/07 true 10-bit multi-channel ADC (F010/11/12/15/16/17). See the Product Selection Guide in Table 1.1 for a quick ...

  • Page 9

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 1.1. C8051F000/05/10/15 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit ...

  • Page 10

    Figure 1.2. C8051F001/06/11/16 Block Diagram VDD VDD Digital Power DGND DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit Internal Oscillator ...

  • Page 11

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 1.3. C8051F002/07/12/17 Block Diagram VDD VDD Digital Power DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit Internal Oscillator ...

  • Page 12

    TM 1.1. CIP-51 CPU 1.1.1. Fully 8051 Compatible The C8051F000 family utilizes Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully TM compatible with the MCS-51 instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. ...

  • Page 13

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.1.3. Additional Features The C8051F000 MCU family has several key enhancements both inside and outside the CIP-51 core to improve its overall performance and ease of use in the end applications. The extended interrupt handler provides 21 interrupt ...

  • Page 14

    On-Board Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct ...

  • Page 15

    ... All the peripherals (except for the ADC) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them in sync. The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the hardware and software necessary to develop application code and perform in-circuit debug with the C8051F000/1/2, F005/6/7, F010/1/2, and F015/6/7 MCUs respectively. The kit includes software with a developer’ ...

  • Page 16

    Programmable Digital I/O and Crossbar The standard 8051 Ports ( and 3) are available on the MCUs. All four ports are pinned out on the F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and ...

  • Page 17

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.5. Programmable Counter Array The C8051F000 MCU family has an on-board Programmable Counter/Timer Array (PCA) in addition to the four 16-bit general-purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer timebase with 5 programmable capture/compare modules. The ...

  • Page 18

    Analog to Digital Converter The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of 1LSB. The ...

  • Page 19

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.8. Comparators and DACs The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is not bonded out on the F002, F007, F012, and F017). The MCU data and control interface ...

  • Page 20

    ABSOLUTE MAXIMUM RATINGS* Ambient temperature under bias................................................................................................................. -55 to 125C Storage Temperature .................................................................................................................................. -65 to 150C Voltage on any Pin (except VDD and Port I/O) with respect to DGND ................................... -0.3V to (VDD + 0.3V) Voltage on any Port ...

  • Page 21

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 4. PINOUT AND PACKAGE DEFINITIONS Pin Numbers F000 F001 F002 Name Type F005 F006 F007 F010 F011 F012 F015 F016 F017 VDD 31, 23, 18, 40 DGND 30, 22, 17, 41, 33 27, ...

  • Page 22

    Pin Numbers F000 F001 F002 Name Type F005 F006 F007 F010 F011 F012 F015 F016 F017 AIN6 AIN7 P0 P0 P0.2 D ...

  • Page 23

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 4.1. TQFP-64 Pinout Diagram 1 CP1- CP1+ 2 CP0- 3 CP0+ 4 AGND 5 VRE F 6 AIN0 7 AIN1 8 AIN2 9 AIN3 10 AIN4 11 12 AIN5 AIN6 13 AIN7 14 AGND 15 AV+ 16 ...

  • Page 24

    Figure 4.2. TQFP-64 Package Drawing PIN 1 DESIGNATOR C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Rev. 1.7 MIN NOM (mm) ( 0.17 0. 12.00 ...

  • Page 25

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 4.3. TQFP-48 Pinout Diagram CP0- 1 CP0+ 2 VREF 3 AIN0 4 AIN1 5 AIN2 6 AIN3 7 AIN4 8 AIN5 9 AIN6 10 AIN7 11 AGND 12 25 C8051F001 C8051F006 C8051F011 C8051F016 Rev. 1.7 P0.3 36 ...

  • Page 26

    Figure 4.4. TQFP-48 Package Drawing PIN 1 IDENTIFIER C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Rev. 1.7 MIN NOM MAX (mm) (mm) (mm ...

  • Page 27

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 4.5. LQFP-32 Pinout Diagram 1 CP0- CP0+ 2 VREF 3 4 AIN0 AIN1 5 6 AIN2 AIN3 7 8 AGND 27 C8051F002 C8051F007 C8051F012 C8051F017 Rev. 1.7 24 P0.3 23 P0.2 22 P0.1 21 DGND 20 VDD ...

  • Page 28

    Figure 4.6. LQFP-32 Package Drawing PIN 1 IDENTIFIER C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 MIN (mm 0. 1. Rev. 1.7 NOM MAX (mm) ...

  • Page 29

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only) The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see ...

  • Page 30

    ADC Modes of Operation The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC conversion ...

  • Page 31

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.3. Temperature Sensor Transfer Function (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 -50 Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t ...

  • Page 32

    Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMXAD3-0: AMUX Address Bits 0000-1111: ADC Inputs selected per chart below 0000 0001 ...

  • Page 33

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x) R/W R/W R/W ADCSC2 ADCSC1 ADCSC0 Bit7 Bit6 Bit5 Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits 000: SAR Conversion Clock = 1 System Clock 001: SAR Conversion Clock = 2 ...

  • Page 34

    Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) R/W R/W R/W ADCEN ADCTM ADCINT Bit7 Bit6 Bit5 Bit7: ADCEN: ADC Enable Bit 0: ADC Disabled. ADC is in low power shutdown. 1: ADC Enabled. ADC is active and ready for data ...

  • Page 35

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC Data Word Bits For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word. For ADLJST = 0: Bits7-4 are ...

  • Page 36

    ADC Programmable Window Detector The ADC programmable window detector is very useful in many applications. It continuously compares the ADC output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is especially effective in ...

  • Page 37

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0x0FFF ADWINT not affected 0x0201 REF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/4096) 0x0100 ...

  • Page 38

    Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0xFFF0 ADWINT not affected 0x2010 REF x (512/4096) 0x2000 ADC0LTH:ADC0LTL 0x1FF0 ADWINT=1 0x1010 REF x (256/4096) 0x1000 ADC0GTH:ADC0GTL 0x0FF0 ...

  • Page 39

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 5.1. 12-Bit ADC Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40C to +85C unless otherwise specified. PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error ...

  • Page 40

    ADC (10-Bit, C8051F010/1/2/5/6/7 Only) The ADC subsystem for the C8051F010/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram ...

  • Page 41

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 6.2. ADC Modes of Operation The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ...

  • Page 42

    Figure 6.3. Temperature Sensor Transfer Function (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 -50 Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: ...

  • Page 43

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMXAD3-0: AMUX Address Bits 0000-1111: ADC Inputs selected per chart below ...

  • Page 44

    Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x) R/W R/W R/W ADCSC2 ADCSC1 ADCSC0 Bit7 Bit6 Bit5 Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits 000: SAR Conversion Clock = 1 System Clock 001: SAR Conversion Clock = 2 System Clocks ...

  • Page 45

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) R/W R/W R/W ADCEN ADCTM ADCINT Bit7 Bit6 Bit5 Bit7: ADCEN: ADC Enable Bit 0: ADC Disabled. ADC is in low power shutdown. 1: ADC Enabled. ADC is active and ready ...

  • Page 46

    Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC Data Word Bits For ADLJST = 1: Upper 8-bits of the 10-bit ADC Data Word. For ADLJST = 0: Bits7-2 are the sign ...

  • Page 47

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 6.3. ADC Programmable Window Detector The ADC programmable window detector is very useful in many applications. It continuously compares the ADC output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is especially ...

  • Page 48

    Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0x03FF ADWINT not affected 0x0201 REF x (512/1024) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/1024) 0x0100 ADC0GTH:ADC0GTL 0x00FF ...

  • Page 49

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 ADWINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 ...

  • Page 50

    Table 6.1. 10-Bit ADC Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40C to +85C unless otherwise specified. PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale ...

  • Page 51

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 7. DACs, 12 BIT VOLTAGE MODE The C8051F000 MCU family has two 12-bit voltage-mode Digital to Analog Converters. Each DAC has an output swing VREF-1LSB for a corresponding input code range of 0x000 to 0xFFF. ...

  • Page 52

    Figure 7.2. DAC0H: DAC0 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 7.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. ...

  • Page 53

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 7.5. DAC1H: DAC1 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 7.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least ...

  • Page 54

    Table 7.1. DAC Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, REF = 2.40V (REFBE=0), No Output Load unless otherwise specified. PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity For Data Word Range 0x014 to 0xFEB Differential Nonlinearity Guaranteed Monotonic (codes 0x014 ...

  • Page 55

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 8. COMPARATORS The MCU family has two on-chip analog voltage comparators as shown in Figure 8.1. The inputs of each Comparator are available at the package pins. The output of each comparator is optionally available at the package ...

  • Page 56

    Figure 8.2. Comparator Hysteresis Plot CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYSP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 OUT Negative Hysteresis Disabled Maximum Positive ...

  • Page 57

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 8.3. CPT0CN: Comparator 0 Control Register R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator 0 Enable Bit 0: Comparator 0 Disabled. 1: Comparator 0 Enabled. Bit6: CP0OUT: Comparator 0 Output State Flag 0: ...

  • Page 58

    Figure 8.4. CPT1CN: Comparator 1 Control Register R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator 1 Enable Bit 0: Comparator 1 Disabled. 1: Comparator 1 Enabled. Bit6: CP1OUT: Comparator 1 Output State Flag 0: Voltage on ...

  • Page 59

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 8.1. Comparator Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, -40C to +85C unless otherwise specified. PARAMETER Response Time1 (CP+) – (CP-) = 100mV (Note 1) Response Time2 (CP+) – (CP-) = 10mV (Note 1) Common Mode ...

  • Page 60

    VOLTAGE REFERENCE The voltage reference circuit consists of a 1.2V, 15ppm/C (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. The reference voltage on VREF can be connected to external devices in the system, as long as ...

  • Page 61

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 9.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care Bit2: TEMPE: Temperature Sensor Enable Bit 0: Internal Temperature Sensor Off. 1: Internal Temperature ...

  • Page 62

    CIP-51 CPU The MCUs’ system CPU is the CIP-51. The CIP-51 is fully compatible with the MCS-51 Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included ...

  • Page 63

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...

  • Page 64

    Refer to Section 11 (Flash Memory) for further details. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 64 ...

  • Page 65

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 10.1. CIP-51 Instruction Set Summary Mnemonic Description ADD A,Rn Add register to A ADD A,direct Add direct byte to A ADD A,@Ri Add indirect RAM to A ADD A,#data Add immediate to A ADDC A,Rn Add register ...

  • Page 66

    Mnemonic Description RRC A Rotate A right through carry SWAP A Swap nibbles of A MOV A,Rn Move register to A MOV A,direct Move direct byte to A MOV A,@Ri Move indirect RAM to A MOV A,#data Move immediate to ...

  • Page 67

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Mnemonic Description ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect ...

  • Page 68

    MEMORY ORGANIZATION The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...

  • Page 69

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 PROGRAM MEMORY 0x807F 128 Byte ISP FLASH 0x8000 0x7FFF RESERVED 0x7E00 0x7DFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 10.2.5. Stack A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is ...

  • Page 70

    SPECIAL FUNCTION REGISTERS The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the SFRs found in a ...

  • Page 71

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Address Register Description 0xC7 ADC0LTH ADC Less-Than Data Word (High Byte) 0xC6 ADC0LTL ADC Less-Than Data Word (Low Byte) 0xBA AMX0CF ADC MUX Configuration 0xBB AMX0SL ADC MUX Channel Selection 0xF0 B B Register 0x8E CKCON Clock Control ...

  • Page 72

    Address Register Description 0xEE PCA0CPL4 PCA Capture Module 4 Data Word (Low Byte) 0xDA PCA0CPM0 Programmable Counter Array 0 Capture/Compare 0 0xDB PCA0CPM1 Programmable Counter Array 0 Capture/Compare 1 0xDC PCA0CPM2 Programmable Counter Array 0 Capture/Compare 2 0xDD PCA0CPM3 Programmable ...

  • Page 73

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Address Register Description 0x89 TMOD Counter/Timer Mode 0x91 TMR3CN Timer 3 Control 0x95 TMR3H Timer 3 High 0x94 TMR3L Timer 3 Low 0x93 TMR3RLH Timer 3 Reload High 0x92 TMR3RLL Timer 3 Reload Low 0xFF WDTCN Watchdog Timer ...

  • Page 74

    Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case ...

  • Page 75

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.6. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation results in a carry (addition borrow (subtraction). It ...

  • Page 76

    Figure 10.7. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits 7-0: ACC: Accumulator This register is the accumulator for arithmetic operations. Figure 10. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits ...

  • Page 77

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.4. INTERRUPT HANDLER The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific ...

  • Page 78

    Table 10.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B Serial Port (UART) 0x0023 Timer 2 Overflow (or EXF2) 0x002B Serial Peripheral ...

  • Page 79

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.4.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for ...

  • Page 80

    Figure 10.10. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don’t care. Bit5: PT2 Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupts. ...

  • Page 81

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ECP1R ECP1F ECP0R Bit7 Bit6 Bit5 Bit7: ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 Rising ...

  • Page 82

    Figure 10.12. EIE2: Extended Interrupt Enable 2 R/W R/W R/W EXVLD - EX7 Bit7 Bit6 Bit5 Bit7: EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt. This bit sets the masking of the XTLVLD interrupt. 0: Disable all XTLVLD interrupts. 1: ...

  • Page 83

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.13. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PCP1R PCP1F PCP0R Bit7 Bit6 Bit5 Bit7: PCP1R: Comparator 1 (CP1) Rising Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 rising interrupt ...

  • Page 84

    Figure 10.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W PXVLD - PX7 Bit7 Bit6 Bit5 Bit7: PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control. This bit sets the priority of the XTLVLD interrupt. 0: XTLVLD interrupt set to ...

  • Page 85

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.5. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, ...

  • Page 86

    If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to sleep for longer than the MCD timeout of ...

  • Page 87

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 11. FLASH MEMORY These devices include 32k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non- volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the ...

  • Page 88

    Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...

  • Page 89

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 11.2. Flash Program Memory Security Bytes Program Memory Space FLASH Read Lock Byte Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.) 0: Read operations are locked (disabled) for corresponding block across the ...

  • Page 90

    MOVC instruction. (Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) Software running in the ...

  • Page 91

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 11.4. FLSCL: Flash Memory Timing Prescaler R/W R/W R/W FOSE FRAE - Bit7 Bit6 Bit5 Bit7: FOSE: Flash One-Shot Timer Enable 0: Flash One-shot timer disabled. 1: Flash One-shot timer enabled Bit6: FRAE: Flash Read Always Enable ...

  • Page 92

    EXTERNAL RAM (C8051F005/06/07/15/16/17) The C8051F005/06/07/15/16/17 MCUs include 2048 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using ...

  • Page 93

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 13. RESET SOURCES The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the CIP-51 halts program execution, forces the external port pins to ...

  • Page 94

    Power-on Reset The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for ...

  • Page 95

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 13.4. External Reset The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting an active-low signal on the /RST pin will cause the MCU to enter the reset state. ...

  • Page 96

    Watchdog Usage The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is generated. ...

  • Page 97

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 13.4. RSTSRC: Reset Source Register R R/W R/W JTAGRST CNVRSEF C0RSEF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations on this register.) Bit7: JTAGRST. JTAG Reset Flag. 0: JTAG is not currently in reset state. 1: ...

  • Page 98

    Table 13.1. Reset Electrical Characteristics -40C to +85C unless otherwise specified. PARAMETER /RST Output Low Voltage I = 8.5mA, VDD = 2.7 to 3.6V OL /RST Input High Voltage /RST Input Low Voltage /RST Input Leakage Current /RST = 0.0V ...

  • Page 99

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 14. OSCILLATOR Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the system clock. The MCUs boot from the internal oscillator after any reset. The internal oscillator starts up instantly. ...

  • Page 100

    Figure 14.2. OSCICN: Internal Oscillator Control Register R/W R/W R/W MSCLKE - - Bit7 Bit6 Bit5 Bit7: MSCLKE: Missing Clock Enable Bit 0: Missing Clock Detector Disabled 1: Missing Clock Detector Enabled; triggers a reset if a missing clock is ...

  • Page 101

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 14.3. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag (Valid only when XOSCMD = 1xx.) 0: Crystal Oscillator is unused or not yet stable 1: ...

  • Page 102

    External Crystal Example If a crystal or ceramic resonator were used to generate the system clock for the MCU, the circuit would be as shown in Figure 14.1, Option 1. For an ECS-110.5-20-4 crystal, the resonate frequency is 11.0592MHz, ...

  • Page 103

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 15. PORT INPUT/OUTPUT The MCUs have a wide array of digital resources, which are available through four digital I/O ports, P0, P1, P2 and P3. Each of the pins on Ports 0, 1, and 2 can be defined ...

  • Page 104

    Port I/O. Furthermore, the weak pullup is turned off on an open-drain output that is driving avoid unnecessary power dissipation. The third and final step is to initialize the individual resources selected using ...

  • Page 105

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 15.1. Crossbar Priority Decode P0 PIN I  SDA  SCL   SCK   MISO   MOSI   NSS    TX    RX ...

  • Page 106

    Figure 15.3. XBR0: Port I/O CrossBar Register 0 R/W R/W R/W CP0OEN ECIE PCA0ME Bit7 Bit6 Bit5 Bit7: CP0OEN: Comparator 0 Output Enable Bit 0: CP0 unavailable at Port pin. 1: CP0 routed to Port Pin. Bit6: ECIE: PCA0 Counter ...

  • Page 107

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.4. XBR1: Port I/O CrossBar Register 1 R/W R/W R/W SYSCKE T2EXE T2E Bit7 Bit6 Bit5 Bit7: SYSCKE: SYSCLK Output Enable Bit 0: SYSCLK unavailable at Port pin. 1: SYSCLK output routed to Port Pin. Bit6: T2EXE: ...

  • Page 108

    Figure 15.5. XBR2: Port I/O CrossBar Register 2 R/W R/W R/W XBARE - WEAKPUD Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable Bit 0: Weak Pull-ups Enabled (except for Ports whose I/O are configured as push-pull) 1: Weak ...

  • Page 109

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 15.3. General Purpose Port I/O Each MCU has four byte-wide, bi-directional parallel ports that can be used general purpose I/O. Each port is accessed through a corresponding special function register (SFR) that is both byte addressable and bit ...

  • Page 110

    Figure 15.8. P1: Port1 Register R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0] (Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers) 0: Logic Low Output. 1: Logic High Output (high-impedance if corresponding ...

  • Page 111

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.11. P2: Port2 Register R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit Bits7-0: P2.[7:0] (Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers) 0: Logic Low Output. 1: Logic High Output (high-impedance ...

  • Page 112

    Figure 15.13. P3: Port3 Register R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7-0: P3.[7:0] (Write) 0: Logic Low Output. 1: Logic High Output (high-impedance if corresponding PRT3CF.n bit = 0) (Read) 0: P3.n is logic low. 1: P3.n ...

  • Page 113

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16. SMBus / I2C Bus The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1. two-wire, bi-directional serial bus, which is also compatible with the I interface by the system ...

  • Page 114

    Figure 16.2 shows a typical SMBus configuration. The SMBus interface will work at any voltage between 3.0V and 5.0V and different devices on the bus may operate at different voltage levels. The SCL (serial clock) and SDA (serial data) lines ...

  • Page 115

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.2. Operation A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of data, and a STOP condition. The address byte and each of the data bytes are followed by ...

  • Page 116

    Slave Receiver Mode Serial data is received on SDA while the serial clock is received on SCL. First, a byte is received that contains an address and data direction bit. In this case the data direction bit (R/W) will ...

  • Page 117

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.1. Control Register The SMBus Control register SMB0CN is used to configure and control the SMBus interface. All of the bits in the register can be read or written by software. Two of the control bits are also ...

  • Page 118

    Figure 16.4. SMB0CN: SMBus Control Register R R/W R/W BUSY ENSMB STA Bit7 Bit6 Bit5 Bit7: BUSY: Busy Status Flag. 0: SMBus is free 1: SMBus is busy Bit6: ENSMB: SMBus Enable. This bit enables/disables the SMBus serial interface. 0: ...

  • Page 119

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.2. Clock Rate Register Figure 16.5. SMB0CR: SMBus Clock Rate Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SMB0CR.[7:0]: SMBus Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master ...

  • Page 120

    Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Data remains stable in the register as long set to logic 1. Software ...

  • Page 121

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus. There are 28 possible SMBus states, each with a corresponding unique status code. The five most significant bits of ...

  • Page 122

    Table 16.1. SMBus Status Codes Status Code Mode (SMB0STA) 0x00 All 0x08 Master Transmitter/Receiver 0x10 Master Transmitter/Receiver 0x18 Master Transmitter 0x20 Master Transmitter 0x28 Master Transmitter 0x30 Master Transmitter 0x38 Master Transmitter 0x40 Master Receiver 0x48 Master Receiver 0x50 Master ...

  • Page 123

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17. SERIAL PERIPHERAL INTERFACE BUS The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports the connection of multiple slave devices to a master device on the same bus. A separate slave-select signal ...

  • Page 124

    Figure 17.2. Typical SPI Interconnection NSS Slave Device Master Device 17.1. Signal Descriptions The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In The master-out, slave-in (MOSI) signal is an output ...

  • Page 125

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17.2. Operation Only a SPI master device can initiate a data transfer. The SPI is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI data register (SPI0DAT) ...

  • Page 126

    In a multiple-master environment, the system controller should check the state of the SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer. 17.3. Serial Clock Timing ...

  • Page 127

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17.4. SPI Special Function Registers The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function ...

  • Page 128

    Figure 17.6. SPI0CN: SPI Control Register R/W R/W R/W SPIF WCOL MODF RXOVRN Bit7 Bit6 Bit5 Bit7: SPIF: SPI Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are ...

  • Page 129

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 17.7. SPI0CKR: SPI Clock Rate Register R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits7-0: SCR7-SCR0: SPI Clock Rate These bits determine the frequency of the SCK output when the SPI module is configured for master ...

  • Page 130

    UART The UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. In all modes, receive data is buffered in a holding register. This allows the UART to start reception of a ...

  • Page 131

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 18.1. UART Operational Modes The UART provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the SCON register. These four modes offer different baud rates and communication protocols. The four modes are ...

  • Page 132

    Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit (see the timing diagram in Figure 18.4). Data are transmitted from ...

  • Page 133

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 The Timer 2 overflow rate, when in Baud Rate Generator Mode and using an internal clock source, is determined solely by the Timer 2 16-bit reload value (RCAP2H:RCAP2L). The Timer 2 clock source is fixed at SYSCLK/2. The ...

  • Page 134

    Mode 2: 9-Bit UART, Fixed Baud Rate Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit ...

  • Page 135

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 18.2. Multiprocessor Communications Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or ...

  • Page 136

    Table 18.2. Oscillator Frequencies for Standard Baud Rates Oscillator Frequency (MHz) 24.0 23.592 22.1184 18.432 16.5888 14.7456 12.9024 11.0592 9.216 7.3728 5.5296 3.6864 1.8432 24.576 25.0 25.0 24.576 24.0 23.592 22.1184 18.432 16.5888 14.7456 12.9024 11.0592 9.216 7.3728 5.5296 3.6864 ...

  • Page 137

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 18.9. SCON: Serial Port Control Register R/W R/W R/W SM0 SM1 SM2 Bit7 Bit6 Bit5 Bits7-6: SM0-SM1: Serial Port Operation Mode. These bits select the Serial Port Operation Mode. SM0 SM1 Mode 0 0 Mode 0: Synchronous ...

  • Page 138

    TIMERS Each MCU implements four counter/timers: three are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit timer for use with the ADC, SMBus, or for general purpose use. These can be used ...

  • Page 139

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD. the input signal /INT0 is logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal ...

  • Page 140

    Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. The TL0 holds the count and TH0 holds the reload value. When the ...

  • Page 141

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is ...

  • Page 142

    Figure 19.4. TCON: Timer Control Register R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when ...

  • Page 143

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.5. TMOD: Timer Mode Register R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled ...

  • Page 144

    Figure 19.6. CKCON: Clock Control Register R/W R/W R T2M Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: T2M: Timer 2 Clock Select. This bit controls the division of the system clock supplied ...

  • Page 145

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 19.8. TL1: Timer 1 Low ...

  • Page 146

    Timer 2 Timer 16-bit counter/timer formed by the two 8-bit SFRs: TL2 (low byte) and TH2 (high byte). As with Timers 0 and 1, Timer 2 can use either the system clock or transitions on an ...

  • Page 147

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.2.1. Mode 0: 16-bit Counter/Timer with Capture In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX input pin causes the 16-bit value in Timer 2 (TH2, TL2) to ...

  • Page 148

    Mode 1: 16-bit Counter/Timer with Auto-Reload The Counter/Timer with Auto-Reload mode sets the TF2 timer overflow flag when the counter/timer register overflows from 0xFFFF to 0x0000. An interrupt is generated if enabled. On overflow, the 16-bit value held in ...

  • Page 149

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.2.3. Mode 2: Baud Rate Generator Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in modes (refer to Section 18.1 for more information ...

  • Page 150

    Figure 19.14. T2CON: Timer 2 Control Register R/W R/W R/W TF2 EXF2 RCLK Bit7 Bit6 Bit5 Bit7: TF2: Timer 2 Overflow Flag. Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000 or reload value. When the Timer 2 ...

  • Page 151

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: RCAP2L: Timer 2 Capture Register Low Byte. The RCAP2L register captures the low byte of Timer 2 when Timer 2 is ...

  • Page 152

    Timer 3 Timer 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). The input for Timer 3 is the system clock (divided by either one or twelve as specified by ...

  • Page 153

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. Timer 3 is configured as an auto-reload timer. This register holds the low byte ...

  • Page 154

    PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array (PCA) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has ...

  • Page 155

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.1. Capture/Compare Modules Each module can be configured to operate independently in one of four operation modes: Edge-triggered Capture, Software Timer, High Speed Output, or Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it ...

  • Page 156

    Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn ...

  • Page 157

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.1.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer is compared to the module’s 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 ...

  • Page 158

    Pulse Width Modulator Mode All of the modules can be used independently to generate pulse width modulated (PWM) outputs on their respective CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The ...

  • Page 159

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.2. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). PCA0H at the same time. By ...

  • Page 160

    Register Descriptions for PCA The system device may implement one or more Programmable Counter Arrays. Following are detailed descriptions of the special function registers related to the operation of the PCA. The CIP-51 System Controller section of the datasheet ...

  • Page 161

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 20.9. PCA0MD: PCA Mode Register R/W R/W R/W CIDL - - Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the ...

  • Page 162

    Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers R/W R/W R/W - ECOMn CAPPn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA ( PCA0CPM1 = 0xDB ( PCA0CPM2 = 0xDC ( PCA0CPM3 = 0xDD (n = ...

  • Page 163

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 20.11. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Figure 20.12. PCA0H: PCA Counter/Timer ...

  • Page 164

    JTAG (IEEE 1149.1) Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing, Flash read and write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE ...

  • Page 165

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 21.1. Boundary Scan The Data Register in the Boundary Scan path is an 87-bit shift register. The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature ...

  • Page 166

    EXTEST Instruction The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature. All inputs to on-chip logic are set ...

  • Page 167

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 21.2. Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register. ...

  • Page 168

    Figure 21.3. FLASHCON: JTAG Flash Control Register WRMD3 WRMD2 WRMD1 Bit7 Bit6 Bit5 This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT Register. Bits7-4: WRMD3-0: Write Mode Select Bits. The Write Mode ...

  • Page 169

    C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 21.5. FLASHDAT: JTAG Flash Data Register DATA7 DATA6 DATA5 DATA4 Bit9 Bit8 Bit7 Bit6 This register is used to read or write data to the Flash memory across the JTAG interface. Bits9-2: DATA7-0: Flash Data Byte. Bit1: ...

  • Page 170

    ... The WDT is disabled when the MCU is halted during single stepping breakpoint. The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the hardware and software necessary to develop application code and perform in-circuit debugging with each MCU in the C8051F000 family ...

  • Page 171

    ... Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 171 Rev ...