C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 62

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

10. CIP-51 CPU
The MCUs’ system CPU is the CIP-51. The CIP-51 is fully compatible with the MCS-51
Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of
all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section
19), a full-duplex UART (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space (see Section 10.3), and four byte-wide I/O Ports (see description in Section 14). The
CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the
MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram). The CIP-51
includes the following features:
-
-
-
-
-
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25MHz Clock
0 to 25MHz Clock Frequency (on ‘F0x5/6/7)
Four Byte-Wide I/O Ports
Extended Interrupt Handler
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
Figure 10.1. CIP-51 Block Diagram
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
TMP2
Rev. 1.7
DATA BUS
DATA BUS
D8
D8
D8
A16
D8
D8
D8
D8
B REGISTER
-
-
-
-
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
SFR
BUS
Reset Input
Power Management Modes
On-chip Debug Circuitry
Program and Data Memory Security
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
TM
instruction set.
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