24LC128-I/SM Microchip Technology, 24LC128-I/SM Datasheet - Page 10

• Manufacturer Part Number: 24LC128-I/SM
• Description: IC EEPROM 128KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC128-I/SM

• Memory Size: 128K (16K x 8)
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 16 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24AA128/24LC128/24FC128
8.0
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24XX128 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
access was to address ‘
next current address read operation would access data
from address
Upon receipt of the control byte with R/W bit set to ‘
the 24XX128 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX128 discontinues transmission (Figure 8-1).
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
DS21191S-page 10
Bus Activity
Master
SDA Line
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
x = “don’t care” bit
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
n + 1
S
S
T
A
R
T
1
1
0
’. Therefore, if the previous read
S 1 0 1 0 A A A 0
S
T
A
R
T
1
Control
.
Byte
0 A A A 1
CURRENT ADDRESS
READ
RANDOM READ
SEQUENTIAL READ
n
1
2 1 0
Control
’ (
’. There are three basic types
Control
Byte
Byte
n
is any legal address), the
2 1 0
A
C
K
A
C
K
A
C
K
Data (n)
x x
Data
Byte
High Byte
Address
N
O
C
A
K
A
C
K
S
T
O
P
1
P
’,
A
C
K
Data (n + 1)
Low Byte
Address
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX128 as part of a write operation (R/W bit set to
‘
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24XX128 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition, which
causes the 24XX128 to discontinue transmission
(Figure 8-2). After a random Read command, the
internal address counter will point to the address
location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24XX128 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX128 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge
but will generate a Stop condition. To provide
sequential reads, the 24XX128 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows the entire memory contents to be serially read
during one operation. The internal Address Pointer will
automatically roll over from address 3FFF to address
0000
from the array address 3FFF.
0’
). Once the word address is sent, the master gener-
A
C
K
if the master acknowledges the byte received
Random Read
Sequential Read
A
C
K
Data (n + 2)
S
T
A
R
T
S 1 0 1 0 A A A 1
Control
Byte
2 1 0
A
C
K
 2010 Microchip Technology Inc.
A
C
K
Data (n + x)
Data
Byte
N
O
A
C
K
S
T
O
P
P
N
O
A
C
K
1
’. The
S
T
O
P
P