24LC128-I/SM Microchip Technology, 24LC128-I/SM Datasheet - Page 9

• Manufacturer Part Number: 24LC128-I/SM
• Description: IC EEPROM 128KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC128-I/SM

• Memory Size: 128K (16K x 8)
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 16 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 6-1:
FIGURE 6-2:
7.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
 2010 Microchip Technology Inc.
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
Master
SDA Line
Bus Activity
x = “don’t care” bit
ACKNOWLEDGE POLLING
BYTE WRITE
PAGE WRITE
S
T
A
R
T
S 1 0 1 0
R
T
A
T
S 1 0 1 0
S
Control
Control
Byte
Byte
A
2
A
2
A
1
A
1
A
0
A
0
0
0
A
C
K
C
A
K
x x
x x
High Byte
High Byte
Address
Address
24AA128/24LC128/24FC128
A
C
K
A
C
K
Low Byte
Address
Low Byte
Address
FIGURE 7-1:
A
C
K
A
C
K
Data Byte 0
Initiate Write Cycle
Send Control Byte
Data
Write Command
with R/W = 0
Condition to
Acknowledge
Send Stop
Send Start
Did Device
(ACK = 0)?
Operation
Send
Next
ACKNOWLEDGE
POLLING FLOW
A
C
K
A
C
K
O
S
T
P
P
Yes
Data Byte 63
x = “don’t care” bit
No
DS21191S-page 9
A
C
K
S
T
O
P
P