AT28HC64B-70TC Atmel, AT28HC64B-70TC Datasheet - Page 5

• Manufacturer Part Number: AT28HC64B-70TC
• Description: IC EEPROM 64KBIT 70NS 28TSOP
• Manufacturer: Atmel

Specifications of AT28HC64B-70TC

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT28HC64B70TC

5.6.1
5.6.2
5.7
5.8
0542F–PEEPR–2/09
Device Identification
Optional Chip Erase Mode
Hardware Protection
Software Data Protection
Hardware features protect against inadvertent writes to the AT28C040 in the following ways:
(a) V
delay – once V
allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
A software controlled data protection feature has been implemented on the AT28C040. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP
disabled.
SDP is enabled when the host system issues a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after t
protected against inadvertent write operations. It should be noted that once protected, the host
can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command
sequence used to enable SDP must precede the data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device, and the
memory addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
t
An extra 256 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
The entire device can be erased using a 6-byte software erase code. Please see Software Chip
Erase application note for details.
WC
, read operations will effectively be polling operations.
CC
sense – if V
CC
has reached 3.8V the device will automatically time out 5 ms (typical) before
CC
is below 3.8V (typical) the write function is inhibited; (b) V
WC
, the entire AT28C040 will be
AT28C040
CC
power-on
5