71V3576S133PFGI

Manufacturer Part Number71V3576S133PFGI
DescriptionSRAM
ManufacturerIDT
SeriesIDT71V3576S
TypeSRAM
71V3576S133PFGI datasheet
 


Specifications of 71V3576S133PFGI

RohsyesOrganization128 K x 36
Access Time4.2 nsSupply Voltage - Max3.465 V
Supply Voltage - Min3.135 VMaximum Operating Current260 mA
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTPackage / CaseTQFP-100
Maximum Clock Frequency133 MHzMemory TypeSynchronous
Part # AliasesIDT71V3576S133PFGI  
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Features
128K x 36, 256K x 18 memory configurations
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
◆ ◆ ◆ ◆ ◆
Self-timed write cycle with global write control (GW), byte write
◆ ◆ ◆ ◆ ◆
enable (BWE), and byte writes (BWx)
3.3V core power supply
◆ ◆ ◆ ◆ ◆
Power down controlled by ZZ input
◆ ◆ ◆ ◆ ◆
3.3V I/O
◆ ◆ ◆ ◆ ◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
◆ ◆ ◆ ◆ ◆
flatpack (TQFP)
Pin Description Summary
A
-A
Address Inputs
0
17
Chip Enable
CE
CS
, CS
Chip Selects
0
1
Output Enable
OE
Global Write Enable
GW
Byte Write Enable
BWE
(1)
Individual Byte Write Selects
BW
, BW
, BW
, BW
1
2
3
4
CLK
Clock
Burst Address Advance
ADV
Address Status (Cache Controller)
ADSC
Address Status (Processor)
ADSP
Linear / Interleaved Burst Order
LBO
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
NOTE:
1. BW
and BW
are not applicable for the IDT71V3578.
3
4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
©2012 Integrated Device Technology, Inc.
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
Description
The IDT71V3576/78 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
1
IDT71V3576S
IDT71V3578S
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
N/A
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
DC
Input
Asynchronous
I/O
Synchronous
Supply
N/A
Supply
N/A
5279 tbl 01
FEBRUARY 2012
DSC-5279/06

71V3576S133PFGI Summary of contents

  • Page 1

    ... SS NOTE and BW are not applicable for the IDT71V3578 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ©2012 Integrated Device Technology, Inc. 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Description The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18 ...

  • Page 2

    ... When OE is HIGH the I/O pins are in a high-impedance state. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the HIGH IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down. N/A 3 ...

  • Page 3

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Functional Block Diagram Commercial and Industrial Temperature Ranges 6.42 3 ...

  • Page 4

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) V Terminal Voltage with TERM Respect to GND (5,6) V Terminal Voltage with -0 ...

  • Page 5

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 DDQ DDQ ...

  • Page 6

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 256K DDQ I I DDQ ...

  • Page 7

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I | LZZ |I | Output Leakage Current ...

  • Page 8

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...

  • Page 9

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 ...

  • Page 10

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters ...

  • Page 11

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 11 ...

  • Page 12

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges , 6.42 12 (1,2,3) ...

  • Page 13

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 14

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 15

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 16

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. ...

  • Page 17

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Ordering Information XXX Power Device Speed Package Type Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) Information available on the IDT website Process/ Temperature ...

  • Page 18

    ... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Datasheet Document History 7/26/99 9/17/99 Pg. 8 Pg. 11 Pg. 18 Pg. 20 12/31/99 Pg 11 11, 19 04/04/00 Pg.18 Pg. 4 Pg. 7 06/01/00 Pg. 20 07/15/00 Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 04/22/03 Pg. 4 06/30/03 Pg. 1,2,3,5-9 Pg. 5-8 Pg. 19,20 Pg. 21-23 Pg. 24 01/01/04 Pg.21 01/20/10 Pg.1,2,4,7,8 Pg.19,20,21 02/25/12 Pg.1,2,3,7,17 CORPORATE HEADQUARTERS ...