CAT1163WI-25-G ON Semiconductor, CAT1163WI-25-G Datasheet - Page 4

• Manufacturer Part Number: CAT1163WI-25-G
• Description: Supervisory Circuits CPU w/16K
• Manufacturer: ON Semiconductor

Specifications of CAT1163WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

1. This parameter is tested initially and after a design or process change that affects the parameter.
2. t
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 6. AC CHARACTERISTICS
V
t
Table 7. POWER−UP TIMING
Table 8. WRITE CYCLE LIMITS
Table 9. RESET CIRCUIT CHARACTERISTICS
BUF
T
t
t
CC
R
PUR
F
Symbol
1
t
t
t
t
t
SU; STO
HD; STA
SU; STA
HD; DAT
SU; DAT
(Note 1)
(Note 1)
F
(Note 1)
t
t
Symbol
Symbol
Symbol
V
HIGH
t
t
= 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.
(Note 1)
LOW
t
V
t
V
GLITCH
PURST
SCL
DH
AA
t
RVALID
t
t
V
V
PUW
and t
t
OHRS
t
PUR
OLRS
RPD
WR
WP
RT
TH
PUW
are the delays required from the time V
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Power−up to Read Operation
Power−up to Write Operation
Write Cycle Time
Glitch Reject Pulse Width
Reset Threshold Hysteresis
Reset Output Low Voltage (I
Reset Output High Voltage
Reset Threshold (V
Reset Threshold (V
Reset Threshold (V
Reset Threshold (V
Reset Threshold (V
Power−Up Reset Timeout
Watchdog Period
V
RESET Output Valid
TH
to RESET Output Delay
(Notes 1 and 2)
CC
CC
CC
CC
CC
= 5 V), (CAT1163−45)
= 5 V), (CAT1163−42)
= 3.3 V), (CAT1163−30)
= 3.3 V), (CAT1163−28)
= 3 V), (CAT1163−25)
Parameter
OLRS
Parameter
Parameter
Parameter
= 1 mA)
CC
http://onsemi.com
is stable until the specific operation can be initiated.
4
V
CC
Min
100
4.7
4.7
4.7
50
4
4
0
4
= 2.7 V − 6 V
V
CC
4.50
4.25
3.00
2.85
2.55
Min
130
Max
100
200
300
15
3.5
− 0.75
1
Min
Min
1
V
CC
Min
100
1.2
0.6
1.2
0.6
0.6
0.6
Typ
Typ
Typ
50
1.6
0
= 4.5 V − 5.5 V
Max
Max
Max
4.75
4.50
3.15
3.00
2.70
100
270
Max
0.4
10
400
200
300
0.3
1
1
5
1
Units
Units
Units
Units
mV
ms
ms
ms
ms
kHz
ns
ms
V
V
V
V
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
s