CAT1163WI-25-G ON Semiconductor, CAT1163WI-25-G Datasheet - Page 7

• Manufacturer Part Number: CAT1163WI-25-G
• Description: Supervisory Circuits CPU w/16K
• Manufacturer: ON Semiconductor

Specifications of CAT1163WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I
follows:
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1163 monitors the SDA and
SCL lines and will not respond until this condition is met.
Acknowledge
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
2
C Bus Protocol
The CAT1163 supports the I
The features of the I
The START Condition precedes all commands to the
After a successful data transfer, each receiving device is
The CAT1163 responds with an acknowledge after
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
FROM TRANSMITTER
FROM RECEIVER
Note: a8, a9 and a10 correspond to the address of the memory array address word.
DATA OUTPUT
DATA OUTPUT
2
C bus protocol are defined as
SCL FROM
MASTER
2
C Bus data transmission
CAT1163
STA
RT
Figure 5. Acknowledge Timing
FUCTIONAL DESCRIPTION
Figure 6. Slave Address Bits
1
http://onsemi.com
1
0
7
1
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are fixed as 1010.
For the CAT1163 the three bits define higher order bits.
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
address byte, the CAT1163 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT1163 then
performs a Read or Write operation depending on the
R/W bit.
responds with an acknowledge after receiving each 8−bit
byte.
bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1163 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
A LOW to HIGH transition of SDA when SCL is HIGH
The Master begins a transmission by sending a START
The next three bits (Figure 6) define memory addressing.
The last bit of the slave address specifies whether a Read
After the Master sends a START condition and the slave
When the CAT1163 begins a READ mode it transmits 8
0
a10
a9
8
a8
ACKNOWLEDGE
R/W
9